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8-channel, 1.5 msps, 12-bit and 10-bit parallel adcs with a sequencer ad7938/ad7939 rev. 0 in fo rmation furn ished by an alog d e v i c e s is believed to be accurate and reliable. how e ver, n o resp on sibili ty is assume d b y a n alog de vices fo r its use, nor for an y i n fri n geme nt s of p a t e nt s or ot h e r ri ght s o f th ird parties th at may result fro m its use . s p ecificatio n s subj ec t to ch an g e witho u t n o tice. no licen s e is g r an te d by implicati o n or ot herwi s e u n der a n y p a t e nt or p a t e nt ri ghts of analog de v i ces. trademarks an d registered tra d ema r ks are the prop erty o f their respective ow ners. one technolog y way, p.o . box 9106, norwood, ma 02062-9106, u.s.a. t e l: 781. 329. 4 700 www.analog.com fax: 781. 326. 87 03 ? 2004 analog de vices, i n c. al l r i ght s r e ser v ed . fea t ures fast throughput rate: 1.5 ms ps specified for v dd of 2.7 v to 5. 25 v low power 6 mw max at 1. 5 msps with 3 v supplies 13.5 mw max a t 1.5 msps wit h 5 v supplies 8 analog input channels with a sequencer software configurable analog inputs 8-channel singl e-ende d inputs 4-channel fu lly differentia l inp u ts 4-channel pseu do-differenti a l inputs 7-channel pseu do-differenti a l inputs accurate on-chip 2.5 v referen c e 0.2% max @ 25c, 25 ppm/c max 70 db sinad at 50 k hz inpu t fr equency n o pipeline delays high speed par a llel interface word/byte modes full sh utdown mode: 2 a m a x 32-lea d lfcsp and tqfp pack age func ti on a l bl ock di a g r a m 03715-0-001 v in 7 t/h parallel interface/control register sequencer 12-/10-bit sar adc and control i/p mux 2.5v vref db0 db11 v drive v dd ad7938/ad7939 v in 0 agnd v refin/ v refout clkin busy convst cs dgnd rd wr w/b fi g u r e 1 . gener a l description the ad7938/ad7939 a r e 12-b i t a nd 10-b i t, hig h s p e e d , lo w p o w e r , successi v e a p p r o x im a t ion (sar) ad cs. the p a r t s o p era t e f r o m a s i n g le 2.7 v t o 5. 25 v p o w e r s u p p l y a n d f e a t ur e thr o ug h p u t ra t e s u p t o 1.5 ms p s . th e p a r t s con t a i n a lo w n o is e , wid e b a n d wi d t h , dif f er en t i a l t r a c k-and- h o ld am plif ier t h a t can ha nd le in p u t f r e q uen c ies u p t o 50 mh z. the ad7938/ad7939 f e a t ur e eig h t a n alog in p u t c h a n n e ls wi th a c h a n ne l s e q u e n cer tha t al lo w a p r ep r o g r a mme d s e le c t io n o f cha n n e ls t o b e c o n v er t e d s e q u e n t i al l y . th e s e p a r t s ca n o p er a t e wi t h e i t h er si n g le-e n d e d , f u l l y dif f er en t i al , o r ps eudo- d i f f er en ti al a n alog i n p u t s . the con v ersio n p r o c es s an d da t a acq u isi t ion a r e co n t r o l l e d usin g st anda r d co n t r o l in pu ts t h a t a l lo w e a sy i n t e r f acin g w i t h micr o p r o cess o r s a nd dsp s . t h e in p u t sig n a l is s a m p le d on t h e fallin g edg e o f co n v s t a nd t h e con v ersio n is a l s o ini t i a te d a t t h is p o in t. the ad7938/ad7939 ha v e a n acc u ra t e on-c hi p 2.5 v r e f e r e n c e th a t ca n be use d a s th e r e f e r e n c e so ur ce f o r th e a n alog- t o- d i g i tal co n v ersio n . a l t e r n a t i v e l y , t h is p i n can b e o v er dr i v en t o p r o v ide an e x te r n a l re f e re nc e. th e s e p a r t s us e ad van c e d desig n t e chniq u es t o achie ve v e r y l o w p o w e r d i s s i p at i o n at h i g h t h r o u g hp u t r a t e s . t h e y a l s o fe a t ur e f l exi b le p o w e r ma na g e m e n t o p t i on s. a n o n -chi p con t rol r e g i s t er al lo ws t h e us er t o s e t up dif f er en t o p er a t in g co ndi t i o n s , in cl u d in g ana l og in p u t ra n g e and co nf igura t ion, o u t p u t co d i ng, p o w e r ma na ge m e n t , and cha n n e l s e q u e n ci n g . produc t highlight s 1. h i g h t h r o ug h p u t w i t h lo w p o wer co n s um p t io n . 2. eig h t ana l og in p u ts wi t h a channel s e q u en c e r . 3. a c c u ra t e on-c hi p 2.5 v r e f e r e n c e . 4. s o f t w a re c o n f i g u r abl e an a l o g i n put s . si ng l e - e nd e d , p s e u d o - dif f er en t i a l , o r f u l l y dif f er en t i al a n alog in p u t s t h a t a r e s o f t wa r e s e le c t ab le . 5. sing l e -s u p ply op er a t ion wi t h v dr iv e fu n c ti o n . th e v dr iv e f u nc t i on a l l o w s t h e p a r a l l el i n te r f a c e to c o nne c t di re c t ly to 3 v , o r 5 v p r o c es s o r sys t em s indep e n d en t o f v dd . 6. n o p i p e lin e de l a y . 7. a c c u ra t e con t r o l o f t h e s a m p ling in st an t v i a a co n v s t i n put a n d o n c e of f c o n v e r s i on c o n t ro l.
ad7938/ad7939 rev. 0 | page 2 of 32 table of contents ad7938specifications .................................................................. 3 ad7939specifications .................................................................. 5 timing specifications ....................................................................... 7 absolute maximum ratings ............................................................ 8 esd caution .................................................................................. 8 pin configuration and function description .............................. 9 te r m i no l o g y .................................................................................... 11 typical performance characteristics ........................................... 13 on-chip registers .......................................................................... 15 control register .......................................................................... 15 sequencer operation ................................................................. 16 shadow register .......................................................................... 16 circuit information ........................................................................ 17 converter operation .................................................................. 17 adc transfer function ............................................................. 17 typical connection diagram ................................................... 18 analog input structure .............................................................. 18 analog inputs .............................................................................. 19 analog input selection .............................................................. 21 reference section ....................................................................... 22 parallel interface ......................................................................... 24 power modes of operation ....................................................... 27 power vs. throughput rate ....................................................... 28 microprocessor interfacing ....................................................... 28 application hints ........................................................................... 30 grounding and layout .............................................................. 30 pcb design guidelines for chip scale package .................... 30 evaluating the ad7938/ad7939 performance ...................... 30 outline dimensions ....................................................................... 31 ordering guide .......................................................................... 32 revision history 10/04revision 0: initial version
ad7938/ad7939 rev. 0 | page 3 of 32 ad7938specifications v dd = v drive = 2.7 v to 5.25 v, internal/external v ref = 2.5 v, unless otherwise noted, f clkin = 25.5 mhz, f sample = 1.5 msps; t a = t min to t max , unless otherwise noted. table 1. parameter b version 1 unit test conditions/comments dynamic performance f in = 50 khz sine wave signal-to-noise + distortion (sinad) 2 70 db min differential mode 68 db min single-ended mode signal-to-noise ratio (snr) 2 71 db min differential mode 69 db min single-ended mode total harmonic distortion (thd) 2 ?73 db max ?85 db typ, differential mode ?70 db max ?80 db typ, single-ended mode peak harmonic or spurious noise (sfdr) 2 ?73 db max ?82 db typ intermodulation distortion (imd) 2 fa = 30 khz, fb = 50 khz second-order terms ?86 db typ third-order terms ?90 db typ channel-to-channel isolation ?85 db typ f in = 50 khz, f noise = 300 khz aperture delay 2 5 ns typ aperture jitter 2 72 ps typ full power bandwidth 2 50 mhz typ @ 3 db 10 mhz typ @ 0.1 db dc accuracy resolution 12 bits integral nonlinearity 2 1 lsb max differential mode 1.5 lsb max single-ended mode differential nonlinearity 2 differential mode 0.95 lsb max guaranteed no missed codes to 12 bits single-ended mode ?0.95/+1.5 lsb max guaranteed no missed codes to 12 bits single-ended and pseudo-differential inp ut straight binary output coding offset error 2 6 lsb max offset error match 2 1 lsb max gain error 2 3 lsb max gain error match 2 1 lsb max fully differential input tw os complement output coding positive gain error 3 3 lsb max positive gain error match 2 1 lsb max zero-code error 2 6 lsb max zero-code error match 2 1 lsb max negative gain error 2 3 lsb max negative gain error match 2 1 lsb max analog input single-ended input range 0 to v ref or 0 to 2 v ref v range bit = 0, or range bit =1, respectively pseudo-differential input range: v in+ 0 to v ref or 2 v ref v range bit = 0, or range bit =1, respectively v in? ?0.3 to +0.7 v typ v dd = 3 v ?0.3 to +1.8 v typ v dd = 5 v fully differential input range: v in+ and v in? v cm v ref /2 v v cm = common-mode voltage 3 = v ref /2 v in+ and v in? v cm v ref v v cm = v ref , v in+ or v in? must remain within gnd/v dd dc leakage current 4 1 a max input capacitance 45 pf typ when in track 10 pf typ when in hold
ad7938/ad7939 rev. 0 | page 4 of 32 parameter b version 1 unit test conditions/comments reference input/output v ref input voltage 5 2.5 v 1% for specified performance dc leakage current 1 a max v ref input impedance 10 k? typ v refout output voltage 2.5 v 0.2% max @ 25c v refout temperature coefficient 25 ppm/c max 5 ppm/c typ v ref noise 10 v typ 0.1 hz to 10 hz bandwidth 130 v typ 0.1 hz to 1 mhz bandwidth v ref output impedance 10 ? typ v ref input capacitance 15 pf typ when in track 25 pf typ when in hold logic inputs input high voltage, v inh 2.4 v min input low voltage, v inl 0.8 v max input current, i in 5 a max typically 10 na, v in = 0 v or v drive input capacitance, c in 4 10 pf max logic outputs output high voltage, v oh 2.4 v min i source = 200 a output low voltage, v ol 0.4 v max i sink = 200 a floating-state leakage current 3 a max floating-state output capacitance 4 10 pf max output coding coding bit = 0 straight (natural) binary twos complement coding bit = 1 conversion rate conversion time t 2 + 13 t clk ns track-and-hold acquisition time 125 ns max full-scale step input throughput rate 1.5 msps max power requirements v dd 2.7/5.25 v min/max v drive 2.7/5.25 v min/max i dd 6 digital i/p s = 0 v or v drive normal mode (static) 0.8 ma typ v dd = 2.7 v to 5.25 v, sclk on or off normal mode (operational) 2.7 ma max v dd = 4.75 v to 5.25 v 2.0 ma max v dd = 2.7 v to 3.6 v autostandby mode 0.3 ma typ f sample = 100 ksps, v dd = 5 v 160 a typ (static) full/autoshutdown mode (static) 2 a max sclk on or off power dissipation normal mode (operational) 13.5 mw max v dd = 5 v 6 mw max v dd = 3 v autostandby mode (static) 800 w typ v dd = 5 v 480 w typ v dd = 3 v full/autoshutdown mode (static) 10/6 w max v dd = 5 v/3 v 1 temperature ranges as follows: b versions: ?40c to +85c. 2 see the terminology section. 3 for full common-mode range, see fi and . gure 25 figure 26 4 sample tested during initial release to ensure compliance. 5 this device is operational with an exte rnal reference in the range 0.1 v to v dd . see the reference section for more information. 6 measured with a midscale dc analog input.
ad7938/ad7939 rev. 0 | page 5 of 32 ad7939specifications v dd = v drive = 2.7 v to 5.25 v, internal/external v ref = 2.5v, unless otherwise noted, f clkin = 25.5 mhz, f sample = 1.5 msps; t a = t min to t max , unless otherwise noted. table 2. parameter b version 1 unit test conditions/comments dynamic performance f in = 50 khz sine wave signal-to-noise + distortion (sinad) 2 61 db min differential mode 60 db min single-ended mode total harmonic distortion (thd) 2 ?70 db max peak harmonic or spurious noise (sfdr) 2 ?72 db max intermodulation distortion (imd) 2 fa = 30 khz, fb = 50 khz second-order terms ?86 db typ third-order terms ?90 db typ channel-to-channel isolation ?75 db typ f in = 50 khz, f noise = 300 khz aperture delay 2 5 ns typ aperture jitter 2 72 ps typ full power bandwidth 2 50 mhz typ @ 3 db 10 mhz typ @ 0.1 db dc accuracy resolution 10 bits integral nonlinearity 2 0.5 lsb max differential nonlinearity 2 0.5 lsb max guaranteed no missed codes to 10 bits single-ended and pseudo-differential in put straight binary output coding offset error 2 2 lsb max offset error match 2 0.5 lsb max gain error 2 1.5 lsb max gain error match 2 0.5 lsb max fully differential input tw os complement output coding positive gain error 2 1.5 lsb max positive gain error match 2 0.5 lsb max zero-code error 2 2 lsb max zero-code error match 2 0.5 lsb max negative gain error 2 1.5 lsb max negative gain error match 2 0.5 lsb max analog input single-ended input range 0 to v ref or 0 to 2 v ref v range bit = 0, or range bit =1, respectively pseudo-differential input range: v in+ 0 to v ref or 2 v ref v range bit = 0, or range bit =1, respectively v in? ?0.3 to +0.7 v typ v dd = 3 v ?0.3 to +1.8 v typ v dd = 5 v fully differential input range: v in+ and v in? v cm v ref /2 v v cm = common-mode voltage 3 = v ref /2 v in+ and v in? v cm v ref v v cm = v ref , v in+ or v in? must remain within gnd/v dd dc leakage current 4 1 a max input capacitance 45 pf typ when in track 10 pf typ when in hold reference input/output v ref input voltage 5 2.5 v 1% for specified performance dc leakage current 4 1 a max v refout output voltage 2.5 v 0.2% max @ 25c v refout temperature coefficient 40 ppm/c typ v ref noise 10 v typ 0.1 hz to 10 hz bandwidth 130 v typ 0.1 hz to 1 mhz bandwidth v ref output impedance 10 ? typ
ad7938/ad7939 rev. 0 | page 6 of 32 parameter b version 1 unit test conditions/comments v ref input capacitance 15 pf typ when in track 25 pf typ when in hold logic inputs input high voltage, v inh 2.4 v min input low voltage, v inl 0.8 v max input current, i in 5 a max typically 10 na, v in = 0 v or v drive input capacitance, c in 4 10 pf max logic outputs output high voltage, v oh 2.4 v min i source = 200 a output low voltage, v ol 0.4 v max i sink = 200 a floating-state leakage current 3 a max floating-state output capacitance 4 10 pf max output coding coding bit = 0 straight (natural) binary twos complement coding bit =1 conversion rate conversion time t 2 + 13 t clk ns track-and-hold acquisition time 125 ns max full-scale step input throughput rate 1.5 msps max power requirements v dd 2.7/5.25 v min/max v drive 2.7/5.25 v min/max i dd 6 digital i/p s = 0 v or v drive normal mode (static) 0.8 ma typ v dd = 2.7 v to 5.25 v, sclk on or off normal mode (operational) 2.7 ma max v dd = 4.75 v to 5.25 v 2.0 ma max v dd = 2.7 v to 3.6 v autostandby mode 0.3 ma typ f sample = 100 ksps, v dd = 5 v 160 a typ (static) full/autoshutdown mode (static) 2 a max sclk on or off power dissipation normal mode (operational) 13.5 mw max v dd = 5 v 6 mw max v dd = 3 v autostandby mode (static) 800 w typ v dd = 5 v 480 w typ v dd = 3 v full/autoshutdown mode (static) 10/6 w max v dd = 5 v/3 v 1 temperature ranges as follows: b versions: ?40c to +85c. 2 see the terminology section. 3 for full common-mode range see fig and . ure 25 figure 26 4 sample tested during initial release to ensure compliance. 5 this device is operational with an exte rnal reference in the range 0.1 v to v dd . see the reference section for more details. 6 measured with a midscale dc analog input.
ad7938/ad7939 rev. 0 | page 7 of 32 timing specifications 1 v dd = v drive = 2.7 v to 5.25 v, internal/external v ref = 2.5 v, unless otherwise noted; f clkin = 25.5 mhz, f sample = 1.5 msps; t a = t min to t max , unless otherwise noted. table 3. limit at t min , t max parameter ad7938 ad7939 unit description f clkin 50 50 khz min 25.5 25.5 mhz max t quiet 30 30 ns min minimum time between end of read and start of next conversion, i.e., time from when the data bus goes into three-st ate until the next falling edge of convst . t 1 10 10 ns min convst pulse width. t 2 15 15 ns min convst falling edge to clkin falling edge setup time. t 3 50 50 ns min clkin falling edge to busy rising edge. t 4 0 0 ns min cs to wr setup time. t 5 0 0 ns min cs to wr hold time. t 6 10 10 ns min wr pulse width. t 7 10 10 ns min data setup time before wr . t 8 10 10 ns min data hold after wr . t 9 10 10 ns min new data valid be fore falling edge of busy. t 10 0 0 ns min cs to rd setup time. t 11 0 0 ns min cs to rd hold time. t 12 30 30 ns min rd pulse width. t 13 2 30 30 ns max data access time after rd . t 14 3 3 3 ns min bus relinquish time after rd . 50 50 ns max bus relinquish time after rd . t 15 0 0 ns min hben to rd setup time. t 16 0 0 ns min hben to rd hold time. t 17 10 10 ns min minimum time between reads/writes. t 18 0 0 ns min hben to wr setup time. t 19 10 10 ns min hben to wr hold time. t 20 40 40 ns max clkin falling edge to busy falling edge. t 21 15.7 15.7 ns min clkin low pulse width. t 22 7.8 7.8 ns min clkin high pulse width. 1 sample tested during initial release to ensure compliance. all input signals are specified with tr = tf = 5 ns (10% to 90% of v dd ) and timed from a voltage level of 1.6 v. all timing specifications given above are with a 25 pf load capacitance (see , figure 36, figure 37, and ). figure 35 figure 38 2 the time required for the output to cross 0.4 v or 2.4 v. 3 t 14 is derived from the measured time taken by the data outputs to change 0.5 v. the measured number is then extrapolated back to remove the effects of charging or discharging the 25 pf capacitor. this means that the time, t 14 , quoted in the timing characteristics is the true bus relinquish time of the part and is independent of the bus loading.
ad7938/ad7939 rev. 0 | page 8 of 3 2 absolute maximum ratings t a = 2 5 c , u n l e ss ot he r w i s e not e d. table 4. p a r a m e t e r r a t i n g v dd to agnd/d gnd ?0.3 v to +7 v v drive to agnd/dgnd ?0.3 v to v dd +0.3 v analog input voltage to agnd ?0.3 v to v dd + 0.3 v digital input voltage to dgnd ?0.3 v to +7 v v drive to v dd ?0.3 v to v dd + 0.3 v digital output v o ltage to dgnd ?0.3 v to v drive + 0.3 v v ref i n to agnd ?0.3 v to v dd + 0.3 v agnd to dg nd ?0.3 v to + 0.3 v input current to any pin except supplies 1 10 ma operating tem p erature range commercia l (b version) ?40c to +85c storage temperature range ?65c to +150c junction tempe r ature 150c ja thermal impedance 108.2c/w (lfc sp) 121c/w ( t q f p ) jc thermal impedance 32.71c/w (lfc sp) 45c/w ( t q f p ) lead temperature, soldering reflow tempera ture (10 sec to 30 sec) 255c e s d 1 . 5 k v 1 transient currents of up to 100 ma do not cause s c r latch-up. s t r e s s es a b o v e t h os e lis t e d u n de r a b s o l u t e m a xi m u m r a t i n g s ma y c a us e p e r m a n en t dama ge t o t h e de vice . this is a s t r e s s ra t i n g onl y ; f u n c t i o n al o p era t ion o f t h e de vice a t t h es e o r an y o t h e r con d i t io ns a b o v e t h os e list e d i n t h e o p era t io nal s e c t io n s o f t h is sp e c if ic a t io n is n o t i m pli e d . e x p o sur e t o a b s o l u t e max i m u m ra t i ng co ndi t i on s fo r ex ten d e d p e r i o d s ma y a f fe c t de vice r e l i ab i l i t y . esd caution esd (electrostatic discharge) sensitive device. ele c tr ostatic charg e s as high as 4000 v readily accumulate on the human body and test eq uipment and can discharg e wit h out detection. althou gh this product features proprietary esd protection circu i try, permanent dama ge may occur on devices subjected to high energy electrostatic discharges. theref ore, prop er esd precautions a r e recommended to avoid perform a nce degradation or l o ss of functiona l ity.
ad7938/ad7939 rev. 0 | page 9 of 3 2 pin conf iguration and function description 03715-0-006 db0 1 v driv e 9 dgnd 10 db8 /hbe n 11 db9 12 db1 0 13 db1 1 14 bus y 15 clkin 16 w/ b 32 v dd 31 v in 7 30 v in 6 29 v in 5 28 v in 4 27 v in 3 26 v in 2 25 db1 2 db2 3 db3 4 db4 5 db5 6 db6 7 db7 8 v in 1 24 v in 0 23 v refin /v refout 22 agnd 21 20 19 wr 18 convst 17 ad7938/ad7939 top view (not to scale) rd cs pin 1 identifier f i gure 2. pin config ur ation ta ble 5. pi n f u nct i on d e s c ri pt i o n pin no mnemonic function 1 to 8 db0 to db7 data bits 0 to 7. t h ree-state para llel d i gital i/ o pi ns that provid e the conversi on r e sult and also a l low the co ntrol and shadow reg i sters to be prog rammed. t h ese pins are c o ntrol l e d by cs , rd , and wr . the logic high/low voltage leve ls fo r these pins ar e determined by the v drive input. when reading from the ad7939, the two lsbs (db0 and db1) a r e always 0 and the lsb of th e conversi on result is available on db2. 9 v drive logic power supply input. t h e voltage supp lie d at this pi n determines at wh at voltage the par a lle l interface of the ad7938/ad 7939 operates. this pin should be decoupled to dgnd. the voltage at this pin may be different to that at v dd but should never e x ceed v dd by more than 0.3 v. 10 dgnd digital ground. this is the ground reference point fo r all digital circuitry on the ad7938/ad793 9. this pin should conn ect to the dgnd plane of a system. the dgnd and agnd voltages should id eally b e at the same potential and m u st not be more than 0. 3 v apart, even on a transient basis. 11 db8/hben data bit 8/high byte enable. when w/ b is high, this pin acts as data bit 8, a three-state i/o pin tha t is controlled by cs , rd , and wr . when w/ b is low, this pin acts as th e hi gh byte enable pin. when hben is low, the low byte of data being written to or read f r om the ad7938/ad7939 is on db0 to db7. when hb en is high, the top four bits of the data being written to or read from the ad7938/ad79 39 are on db0 to db3. when re ading from the device, db4 to db6 of the high byte contains the id of the channel to whic h the conversi on resu lt corresp ond s (see the channe l address bits in table 9). when writing to the d evice, db4 to db7 of the high byte must be all 0s. note that when reading from the ad7939, the two lsbs of the low byte are 0s, and the remaini n g 6 bits, conver sion data . 12 to 14 db9 to db11 data bits 9 to 11. t h ree-state par a lle l d i gital i/o p i ns that provid e the conversi on r e sult and also a l low the control a n d sha d ow registers to be programme d in word mode. these pins are c o ntrolled by cs , rd , and wr . the logic high/low voltage levels for these pin s are determined by the v drive input. 15 busy busy output. lo gic output indic a ting the status of the conversi o n . the bu sy output goes high following the falling edge of convst and stays high for the duration of the con versi o n . once the con version i s comp lete and the result is available in the output register, the busy output g o es low. the track- and-hold returns to track mode just prior to the falling edge of busy on the 13 th rising edge of sclk, see figure 35. 16 clkin master clock in put. t h e clock s o urce for the co nversio n pr oc ess is applied to this pin. con versi on time for the ad7938/ad793 9 takes 13 clock cycles + t 2 . the frequency of the master clo c k inp ut therefore determines the conver sion time and achievab l e thro ughput rate. the clkin signal may be a cont inuous or burst clock. 17 convst conversion start input. a fall ing e d ge on convs t is us ed t o ini t ia te a conv e r sion. the track-a n d-hol d goes fro m t r ack to hol d mod e on the falling e d ge of convs t and the conv ersion p r ocess is initi a ted at this p o int. followin g p o wer- d o wn, when op eratin g in a u toshutd o wn or a utos t a n db y mo des, a ri sing e d ge on convs t is used to power- u p the devic e . 18 wr write input. acti ve low logic input used in conj unction with cs to write data to th e internal regist ers. 19 rd read input. acti ve low logic input used in conj unction with cs to access the c o nve r sion re sult. t h e conver sion result is pla c ed on the d a ta bus follo wing the fal l ing ed ge of rd read while cs is lo w.
ad7938/ad7939 rev. 0 | page 10 of 32 pin no mnemonic function 20 cs chip select. active low logic input used in conjunction with rd and wr to read conversion data or to write data to the internal registers. 21 agnd analog ground. this is the ground reference point fo r all analog circuitry on the ad7938/ad7939. all analog input signals and any external reference signal should be referred to this agnd voltage. the agnd and dgnd voltages should ideally be at the sa me potential and must not be more th an 0.3 v apart, even on a transient basis. 22 v refin /v refout reference input/output. this pin is co nnected to the internal reference and is the reference source for the adc. the nominal internal reference voltage is 2.5 v and this appears at this pin. this pin can be overdriven by an external reference. the input voltage range for the external reference is 0.1 v to v dd ; however, care must be taken to ensure that the analog input range does not exceed v dd + 0.3 v. see the reference section. 23 to 30 v in 0 to v in 7 analog input 0 to analog in put 7. eight analog input ch annels that are multiplexed into the on-chip track-and- hold. the analog inputs can be programmed to be eight si ngle-ended inputs, four fully differential pairs, four pseudo-differential pairs, or seven pseudo-differential in puts by setting the mode bits in the control register appropriately (see table 9). the analog input channel to be converted can either be selected by writing to the address bits (add2 to add0) in the control register pr ior to the conversion or the on-chip sequencer can be used. the seq and shdw bits in conjunction with the a ddress bits in the control register allow the shadow register to be programmed. the input range fo r all input channels can either be 0 v to v ref or 0 v to 2 v ref , and the coding can be binary or twos complement, dependin g on the states of the range and coding bits in the control register. any unused inp ut channels should be connected to agnd to avoid noise pickup. 31 v dd power supply input. the v dd range for the ad7938/ad7939 is 2.7 v to 5.25 v. the supply should be decoupled to agnd with a 0.1 f capacitor and a 10 f tantalum capacitor. 32 w/ b word/byte input. when th is input is logic high, data is transfer red to and from the ad7938/ad7939 in 12-bit/10- bit words on pins db0/db2 to db11. wh en this pin is logic low, byte tran sfer mode is enabled. data and the channel id are transferred on pins db0 to db7, and pin db8/hben assumes its hben fu nctionality. unused data lines when operating in byte transfer mode should be tied off to dgnd.
ad7938/ad7939 rev. 0 | page 11 of 32 terminology integral nonlinearity this is the maximum deviation from a straight line passing through the endpoints of the adc transfer function. the endpoints of the transfer function are zero scale, a point 1 lsb below the first code transition, and full scale, a point 1 lsb above the last code transition. differential nonlinearity this is the difference between the measured and the ideal 1 lsb change between any two adjacent codes in the adc. offset error this is the deviation of the first code transition (00 . . .000) to (00 . . . 001) from the ideal, i.e., agnd + 1 lsb. offset error match this is the difference in offset error between any two channels. gain error this is the deviation of the last code transition (111 . . .110) to (111 . . . 111) from the ideal (i.e., v ref C 1 lsb) after the offset error has been adjusted out. gain error match this is the difference in gain error between any two channels. zero-code error this applies when using the twos complement output coding option, in particular to the 2 v ref input range with ?v ref to +v ref biased about the v refin point. it is the deviation of the mid scale transition (all 0s to all 1s) from the ideal v in voltage, i.e., v ref . zero-code error match this is the difference in zero-code error between any two channels. positive gain error this applies when using the twos complement output coding option, in particular to the 2 v ref input range with ?v ref to +v ref biased about the v refin point. it is the deviation of the last code transition (011. . .110) to (011 .. . 111) from the ideal (i.e., +v ref ? 1 lsb) after the zero-code error has been adjusted out. positive gain error match this is the difference in positive gain error between any two channels. negative gain error this applies when using the twos complement output coding option, in particular to the 2 v ref input range with ?v ref to +v ref biased about the v ref point. it is the deviation of the first code transition (100 . . . 000) to (100 . . . 001) from the ideal (i.e., ?v refin + 1 lsb) after the zero-code error has been adjusted out. negative gain error match this is the difference in negative gain error between any two channels. channel-to-channel isolation channel-to-channel isolation is a measure of the level of crosstalk between channels. it is measured by applying a full- scale sine wave signal to all seven nonselected input channels and applying a 50 khz signal to the selected channel. the channel-to-channel isolation is defined as the ratio of the power of the 50 khz signal on the selected channel to the power of the noise signal on the unselected channels that appears in the fft of this channel. the noise frequency on the unselected channels varies from 40 khz to 740 khz. the noise amplitude is at 2 v ref , while the signal amplitude is at 1 v ref . power supply rejection ratio (psrr) psrr is defined as the ratio of the power in the adc output at full-scale frequency, f, to the power of a 100 mv p-p sine wave applied to the adc v dd supply of frequency f s . the frequency of the noise varies from 1 khz to 1 mhz. psrr (db) = 10 log ( pf/pf s ) pf is the power at frequency f in the adc output; pf s is the power at frequency f s in the adc output. common-mode rejection ratio (cmrr) cmrr is defined as the ratio of the power in the adc output at full-scale frequency, f, to the power of a 100 mv p-p sine wave applied to the common-mode voltage of v in+ and v in? of frequency f s as cmrr (db) = 10log( pf/pf s ) pf is the power at frequency f in the adc output; pf s is the power at frequency f s in the adc output. track-and-hold acquisition time the track-and-hold amplifier returns to track mode at the end of conversion. the track-and-hold acquisition time is the time required for the output of the track-and-hold amplifier to reach its final value, within 1/2 lsb, after the end of conversion.
ad7938/ad7939 rev. 0 | page 12 of 32 s i g n a l -t o-(n o i s e + dis t o r t i o n ) r a t i o (s in ad) t h i s i s t h e me a s u r e d r a t i o of s i g n a l - t o - ( n oi s e + d i stor t i on ) a t t h e o u t p ut o f t h e a/ d con v er t e r . th e sig n al is t h e r m s am pli t u d e o f t h e f u ndam e n t a l . n o i s e is t h e s u m o f al l n o nf undam e n t al sig n als u p t o half th e s a m p l i n g f r e q uen c y (f s /2), excl udin g dc. the ra tio is dep e n d en t on t h e n u m b er o f q u an t i za tio n l e v e l s in th e di gi t i za ti o n p r oce s s; th e m o r e lev e l s, th e smalle r th e q u a n tiz a ti o n n o i s e . th e t h eo r e tical si gn al-t o- (n o i se + d i s t o r tio n ) ra tio f o r a n id eal n-b i t co n v er t e r wi th a sin e wa v e in p u t is g i v e n b y sig n al - t o - ( n o i s e + d i s t or t i on ) = (6.02 n + 1.76) db th us, f o r a 12-b i t con v er t e r , this is 74 db , an d f o r a 10-b i t co n v er t e r , this is 62 db . t o t a l ha r m on i c d i s t or t i on ( t h d ) t h d i s th e ra tio o f th e rm s s u m o f h a rm o n i c s t o th e f u ndam e n t al . f o r th e ad7938/ ad7939, i t is def i n e d as () 1 6 5 4 3 2 v v v v v v thd 2 2 2 2 2 20log db + + + + ? = w h er e v 1 i s th e rm s a m p l i t ud e o f th e fun d a m en tal a n d v 2 , v 3 , v 4 , v 5 , a nd v 6 a r e t h e r m s am pli t udes o f t h e s e c o nd t h r o u g h t h e six t h ha r m o n i c s . p e a k h a rmo n i c o r s p uri o us n o is e p e a k ha r m o n ic o r sp ur io us n o is e is def i ne d as t h e r a t i o o f t h e r m s val u e o f t h e n e xt la rg es t com p on e n t i n t h e ad c o u t p ut s p ectr um (u p t o f s /2 an d excl udi n g dc) t o t h e r m s val u e o f t h e f u ndam e n t a l . n o r m a l ly , t h e va lue o f t h is sp e c if ica t ion is det e r m i n e d b y t h e la rg es t ha r m o n ic in t h e sp e c t r um, b u t fo r ad cs w h er e t h e ha r m o n ic s a r e b u r i e d i n t h e no is e f l o o r , i t is a noi s e p e a k . inte r m o d u l at i o n d i s t or t i on w i t h in p u ts co nsis tin g o f sine wa v e s a t tw o f r eq uen c ies, fa and fb , a n y a c t i v e de v i ce wi th n o nlin ea ri ti e s cr e a t e s d i s t o r ti o n p r o d uc ts a t s u m a nd dif f er ence f r e q uen c ies o f mfa nfb w h er e m, n = 0, 1, 2, 3, et c. i n ter m o d u l a t i o n dis t o r t i on t e r m s a r e t h os e f o r wh ic h n e i t h e r m n o r n a r e e q ual t o 0. f o r ex a m p l e , th e seco n d -o r d er t e r m s in c l ude (fa + fb) a n d (fa ? fb), while t h e t h ird-o r d er t e r m s i n cl ude ( 2 fa + fb), (2fa ? fb), (fa + 2fb), a nd ( f a ? 2fb) . the ad7938/ad7939 a r e t e s t e d usin g the cci f s t a n da r d w h er e tw o in p u t f r e q u e n c ies n e a r t h e t o p end o f t h e i n p u t b a n d wi d t h a r e us e d . i n t h i s cas e , t h e s e cond-o r d er t e r m s ar e us ual l y dist an c e d i n f r e q uen c y f r o m t h e o r ig ina l sine wa ves w h i l e t h e t h ir d-o r d er t e r m s a r e us ual l y a t a f r e q uen c y cl os e t o t h e i n p u t f r e q uen c ies. a s a r e su l t , t h e s e c o nd- and t h ir d - o r d er ter m s a r e sp e c if ie d s e p a ra t e l y . th e c a lc u l a t io n o f t h e in t e r m o d u l a t ion dist o r t i o n is a s p e r t h e th d sp e c if ica t ion w h er e i t is t h e ra t i o o f th e rm s s u m o f th e in d i v i d u al di s t o r ti o n p r od uct s t o th e rm s a m pli t ude o f t h e s u m o f t h e f u ndam e n t als expr es s e d i n db s.
ad7938/ad7939 rev. 0 | page 13 of 32 typical perf orm ance cha r acte ristics t a = 25c, unles s o t h e r w is e n o te d . supply ripple frequency (khz) pssr ( d b ) ?60 ?70 ?80 ?90 ? 110 ? 100 ? 120 10 210 610 410 810 1010 03715-0-007 100mv p-p sine wave on v dd and/or v drive no decoupling differential/single-ended mode int ref ext ref f i g u r e 3 . p s r r v s . s u pp l y ripp le f r e q ue n c y w i t h o u t s u pp ly de c o u p l i n g noise frequency (khz) nois e is olation (db) ?70 ?75 ?90 ?85 ?80 ? 195 0 100 400 200 300 600 500 800 700 03715-0-021 internal/external reference v dd = 5v f i g u re 4. a d 79 38 c h ann e l-t o - c hann el is ol at i o n frequency (khz) s i nad (db) 80 70 60 50 40 30 20 0 100 400 200 300 600 500 1000 700 800 900 03715-0-008 f sample = 1.5msps range = 0 to v ref differential mode v dd = 5v v dd = 3v f i g u re 5. a d 79 38 si na d v s . a n al og inp u t f r equ e nc y f o r v a ri ous sup p l y v o lt ag es frequency (khz) 0 ?10 ?20 ?50 ?40 ?30 ?90 ? 100 ?80 ?70 ?60 ? 110 0 100 200 300 400 500 600 700 03715-0-009 4096 point fft v dd = 5v f sample = 1.5msps f in = 49.62khz sinad = 70.94db thd = ? 90.09db differential mode db f i g u re 6. a d 79 38 f f t @ v dd = 5 v code dnl e rror (ls b ) 1.0 0.8 0.6 0.4 0.2 ? 0.2 0 ? 0.8 ? 0.6 ? 0.4 ? 1.0 0 500 2000 1000 1500 3000 2500 4000 3500 03715-0-010 v dd = 5v differential mode f i g u re 7. a d 79 38 t y pic a l d n l @ v dd = 5 v code inl e rror (ls b ) 1.0 0.8 0.6 0.4 0.2 ? 0.2 0 ? 0.8 ? 0.6 ? 0.4 ? 1.0 0 500 2000 1000 1500 3000 2500 4000 3500 03715-0-011 v dd = 5v differential mode f i g u re 8. a d 79 38 t y pic a l inl @ v dd = 5 v
ad7938/ad7939 rev. 0 | page 14 of 32 v ref (v) dnl (ls b ) 6 5 4 3 1 2 0 ?1 0.25 0.50 1.25 0.75 1.00 2.00 1.75 1.50 2.75 2.50 2.25 03715-0-012 single-ended mode positive dnl negative dnl f i g u re 9. a d 79 38 d n l v s . v ref fo r v dd = 3 v v ref (v) e ffe ctiv e numbe r of bits 12 11 10 8 9 7 6 0 0.5 1.5 1.0 2.5 2.0 4.0 3.5 3.0 04751-013 v dd = 5v differential mode v dd = 5v single-ended mode v dd = 3v single-ended mode v dd = 3v differential mode f i gur e 1 0 . ad79 38 enob vs . v ref v ref (v) offset ( l sb ) 0 ? 0.5 ? 1.5 ? 1.0 ? 3.5 ? 3.0 ? 2.5 ? 2.0 ? 4.0 ? 4.5 ? 5.0 0 0.5 1.5 1.0 2.5 2.0 3.5 3.0 03715-0-014 single-ended mode v dd = 5v v dd = 3v f i gur e 1 1 . ad79 38 o ffse t vs . v ref code ??? 10000 9000 7000 8000 3000 4000 5000 6000 2000 1000 0 2046 2047 2048 2049 2050 03715-0-015 differential mode 3 codes internal ref 9997 codes f i gur e 1 2 . ad79 38 h i sto g r a m o f co des fo r 10k s a mpl e s @ v dd = 5 v with the i n te r n al r e ference ripple frequency (khz) cmrr (db) ?60 ?70 ?80 ? 100 ?90 ? 110 ? 120 0 200 400 800 600 1200 1000 03715-0-017 differential mode fi g u r e 1 3 . c m r r v s . i n p u t fr e q u e n c y w i t h v dd = 5 v and 3 v
ad7938/ad7939 rev. 0 | page 15 of 32 on-chip registers the ad7938/ad7939 have two on-chip registers that are necessary fo r the operation of the device. these are the control register , which is used to set up different operating conditions, and the shadow register, which is used to program the analog input channels to b e converted. control register the control register on the ad7938/ad7939 is a 12-bit, write-only register. data is written to this register using the cs and wr pins. the control register is shown below and the functions of the bits are described in table 7. at power up, the default bit settings i n the control register are all 0s. table 6. control register bits msb lsb db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 pm1 pm0 coding ref add2 add1 add0 mode1 mode0 shdw seq range table 7. control register bit function description bit no. mnemonic description 11, 10 pm1, pm0 power management bits. these two bits are used to select the power mo de of operation. the user can choose between either normal mode or various power-down modes of operation as shown in table 8. 9 coding this bit selects the output coding of the conversion result. if this bit is set to 0, th e output coding is straight (natural) binary. if this bit is set to 1, the output coding is twos complement. 8 ref this bit selects whether the internal or external reference is used to perform the conversion. if this bit is logic 0, an external reference should be applied to the v ref pin, and if this bit is logic 1, th e internal reference is selected (see the reference section). 7 to 5 add2 to add0 these three address bits are used to either select which analog input channel is converted in the next conversion if the sequencer is not used, or to se lect the final channel in a consecutive sequence when the sequencer is used as described in table 10. the selected inp ut channel is decoded as shown in table 9. 4, 3 mode1, mode0 the two mode pins select the type of analog input on the eight v in pins. the ad7938/ad7939 can have either eight single-ended inputs, four fully differential inp uts, four pseudo-differentia l inputs, or seven pseudo- differential inputs (see table 9). 2 shdw the shdw bit in the control register is used in conjunction with the seq bit to control the sequencer function and access the shdw register (see table 10). 1 seq the seq bit in the control register is used in conjunctio n with the shdw bit to control the sequencer function and access the shdw register (see table 10). 0 range this bit selects the analog input range of the ad7938/ad7939. if it is set to 0, then th e analog input range extends from 0 v to v ref . if it is set to 1, then the analog input range extends from 0 v to 2 v ref . when this range is selected, av dd must be 4.75 v to 5.25 v if a 2.5 v reference is us ed; otherwise, care must be taken to ensure that the analog input remains within th e supply rails. see analog inputs section for more information. table 8. power mode selection using the power management bits in the control register pm1 pm0 mode description 0 0 normal mode when operating in normal mode, all circuitry is fully powered up at all times. 0 1 autoshutdown when operating in autoshutdown mode, the ad7938/ ad7939 enter full shutdown mode at the end of each conversion. in this mode, all circuitry is powered down. 1 0 autostandby when the ad7938/ad7939 enter this mode , all circuitry is powered down except for the reference and reference buffer. this mode is similar to autoshutdown mode, but it allows the part to power-up in 7 s (or 600 ns if an external reference is used). see the power modes of operation section for more information. 1 1 full shutdown when the ad7938/ad7939 enter this mode , all circuitry is powered down. the information in the control register is retained.
ad7938/ad7939 rev. 0 | page 16 of 32 table 9. analog input type selection channel address mode0 = 0, mode1 = 0 mode0 = 0, mode1 = 1 mode0 = 1, mode1 = 0 mode0 = 1, mode1 = 1 eight single-ended i/p channels four fully differential i/p channels four pseudo-differential i/p channels (pseudo mode 1) seven pseudo-differential i/p channels (pseudo mode 2) add2 add1 add0 v in+ v in- v in+ v in- v in+ v in- v in+ v in- 0 0 0 vin0 agnd vin0 vin1 vin0 vin1 vin0 vin7 0 0 1 vin1 agnd vin1 vin0 vin1 vin0 vin1 vin7 0 1 0 vin2 agnd vin2 vin3 vin2 vin3 vin2 vin7 0 1 1 vin3 agnd vin3 vin2 vin3 vin2 vin3 vin7 1 0 0 vin4 agnd vin4 vin5 vin4 vin5 vin4 vin7 1 0 1 vin5 agnd vin5 vin4 vin5 vin4 vin5 vin7 1 1 0 vin6 agnd vin6 vin7 vin6 vin7 vin6 vin7 1 1 1 vin7 agnd vin7 vin6 vin7 vin6 not allowed sequencer operation the configuration of the seq and shdw bits in the control register allows the user to select a particular mode of operation of the sequencer function. table 10 outlines the four modes of operation of the sequencer. table 10. sequence selection seq shdw sequence type 0 0 this configuration is selected when the sequence function is not used. the analog input channel selected on each individual conversion is determined by the contents of th e channel address bits, add2 to add0, in each prior write operation. this mode of operation refl ects the traditional operation of a mu ltichannel adc, without the sequencer function being used, where each write to the ad 7938/ad7939 selects the next channel for conversion. 0 1 this configuration selects the shadow register for programmi ng. the following write operation loads the data on db0 to db7 to the shadow register. this programs the sequence of channels to be converte d continuously after each convst falling edge (see the shadow register description and table 11). 1 0 if the seq and shadow bits are set in th is way, the sequence function is not in terrupted upon completion of the write operation. this allows other bits in the control register to be altered between conversions while in a sequence without terminating the cycle. 1 1 this configuration is used in conjun ction with the channel address bits (a dd2 to add0) to program continuous conversions on a consecutive sequence of channels from channel 0 through to a selected final channel as determined by the channel address bits in the control register. shadow register the shadow register on the ad7938/ad7939 is an 8-bit, write-only re gister. data is loaded from db0 to db7 on the rising edge of wr . the eight lsbs load into the shadow register. the information is written into the shadow register provided that the seq and shd w bits in the control register were set to 0 and 1, respectively, in the previous write to the control register. each bit represents a n analog input from channel 0 through channel 7. a sequence of channels ma y be selected through which the ad7938/ad7939 cycles with each consecutive conversion after the write to the shadow register. to select a sequence of channels to be converted, if operating i n single- ended mode or pseudo mode 2, the associated channel bit in the shadow register must be set for each required analog input. when operating in differential mode or pseudo mode 1, the associated pair of channels bits must be set for each pair of analog inpu ts required in the sequence. with each consecutive convst pulse after the sequencer has been se t up, the ad7938/ad7939 progress through the selected channels in ascending order, beginning with the lowest channel. this continues until a write operation occurs with the seq and shdw bits configured in any way except 1, 0 (see table 10). when a sequence is set up in differential or pseudo mode 1, the adc does not convert on the inverse pairs (i.e., vin1, vin0). the bit functions of the shadow register are outlined in table 11. see the analog input selection section for further information on using the sequencer. table 11. shadow register bit functions v in 0 v in 1 v in 2 v in 3 v in 4 v in 5 v in 6 v in 7
ad7938/ad7939 rev. 0 | page 17 of 32 circuit i n formation the ad7938/ad7939 a r e fast, 8-c h a n n e l , 12-b i t a nd 10-b i t, s i ng l e -sup ply , su c c e ss ive a p p rox ima t ion ana l o g -to - d i g i t a l co n v er t e rs. th e p a r t s ca n o p er a te f r o m a 2.7 v to 5.25 v p o we r s u pp l y an d f e atu r e t h rou g h put r a te s up to 1 . 5 m s p s . the ad7938/ad7939 p r o v ide th e us er wi t h a n o n -c hi p trac k- and- hol d , an ac c u r a te i n te r n a l re fe re nc e, an ana l o g - t o - di g i t a l c o n v e r te r , and a p a r a l l el i n te r f ac e hou s e d i n a 3 2 - l e a d l f c s p or tqf p p a ck age. the ad7938/ad7939 ha v e eig h t a n alog in p u t c h a n n e ls tha t ca n be co n f i g ur ed t o be e i g h t sin g le - e n d e d in p u t s , f o ur full y dif f er en t i a l p a irs, fo ur ps eudo-dif fer e n t ia l p a irs, o r s e v e n ps eudo-dif fer e n t ial i n p u ts w i t h r e s p e c t t o on e c o mm on i n p u t. ther e is a n on-chi p us er -p r o g r a mma b l e chann e l s e q u e n cer t h a t al lo ws th e us er t o s e lec t a s e q u en ce o f c h a n ne ls thr o u g h which t h e ad c can p r og r e s s a n d c y cle wi t h e a ch co n s e c u t i v e fal l i n g ed g e o f co n v s t . the a n alog in p u t ra n g e f o r th e ad7938/ad79 39 is 0 t o v ref or 0 t o 2 v ref dep e ndin g o n t h e s t a t us o f th e r a n g e b i t in t h e co n t r o l r e g i s t er . the o u t p u t co di n g o f t h e ad c ca n b e e i t h er b i na r y o r tw o s co m p le m e n t , dep e ndin g on t h e st a t us o f t h e co d i n g b i t i n th e co n t r o l r e gi s t e r . the ad7938/ad7939 p r o v ide f l exi b le p o w e r ma na g e m e n t o p t i o n s t o al lo w t h e us er t o achi e v e t h e b e s t p o w e r p e r f o r ma n c e fo r a g i v e n t h r o u g h p u t r a t e . thes e o p t i o n s a r e s e le c t e d b y p r ogra m m i n g t h e po w e r m a n a g e m e n t b i ts, pm1 a n d pm0, in t h e c o n t ro l re g i ste r . converter operation the ad7938/ad7939 a r e s u cc es si v e a p p r o x ima t io n ad cs b a s e d a r o u nd t w o ca p a ci t i ve d a cs. f i gur e 14 a nd f i gur e 15 sh o w si m p lif i e d s c h e ma t i cs o f t h e ad c in a c q u isi t io n and c o n v e r s i on ph a s e, re sp e c t i vely . t h e a d c c o m p r i s e s of c o n t ro l l o gi c , a s a r, a n d t w o ca pa ci ti v e d a c s . b o th f i gu r e s s h o w th e o p era t ion o f t h e ad c in dif f er en t i al/ps e udo- di f f er en t i al m o de . sin g le-e nde d mo de o p er a t io n is simi la r b u t v in ? is in t e r n a l ly t i e d t o a g nd . i n acq u isi t io n ph as e , sw3 is clos e d , sw1 and sw 2 a r e in p o si tio n a, t h e co m p a r a t o r is he ld in a ba lan c e d co ndi t i on, an d t h e s a m p li n g c a p a ci t o r a r ra ys ac q u ir e t h e dif f er en t i al sig n al o n t h e i n p u t . 03715-0-023 v in+ v in? a b sw1 sw3 comparator control logic capacitive dac capacitive dac c s c s v ref sw2 b a f i g u re 14. a d c ac quis it i o n p h as e w h en t h e ad c s t a r ts a con v ersio n (f igur e 15), sw3 o p e n s an d sw 1 a n d sw 2 m o v e t o p o s i ti o n b , ca us i n g th e co m p a r a t o r t o beco m e un bala n c e d . b o th in p u t s a r e d i sco n n e c t ed o n ce t h e co n v ersio n b e g i n s . th e co n t r o l log i c a n d t h e c h a r g e r e dist r i b u t i o n d a cs a r e us e d to add and sub t r a c t f i xe d amou n t s of ch a r ge f rom t h e s a m p l i ng c a p a c i to r ar r a y s to b r in g t h e com p a r a t o r back in t o a bala n c ed co n d i ti o n . w h e n t h e com p a r a t o r is r e b a la nce d , t h e co n v ersion is co m p let e . the co n t r o l log i c g e n e ra t e s t h e ad c s ou t p u t co de . the o u t p u t im p e dan c es o f t h e s o ur ces dr i v i n g t h e v in + and th e v in ? pi n s m u s t ma t c h; o t h e r w is e , t h e two in p u ts ha v e di f f er en t s e t t ling t i me s , w h i c h re su lt i n e r ror s . 03715-0-024 v in+ v in? a b sw1 sw3 comparator control logic capacitive dac capacitive dac c s c s v ref sw2 b a f i g u re 15. a d c co nvers i on p h as e adc tra n s f er func ti on the o u t p u t co din g f o r th e ad79 38/ad7939 is ei th er s t ra ig h t b i na r y o r tw o s co m p le m e n t , dep e ndin g on t h e st a t us o f t h e c o d i n g b i t in t h e con t r o l r e g i s t er . the desig n e d co de t r a n si t i o n s o c c u r a t s u cces s i v e l s b val u es (i .e ., 1 ls b , 2 ls bs, a nd s o o n ) and t h e l s b si ze is v ref /4096 f o r th e ad7938 and v ref /1024 f o r th e ad7939. the ideal tra n sf er c h a r ac t e r i s t ics o f th e ad7938/ad7939 f o r bo t h s t ra ig h t b i na r y a n d tw os co m p le m e n t o u t p u t c o di n g a r e sh own i n f i gur e 16 a nd f i g u re 1 7 , re sp e c t i vely . 03715-0-025 000...000 111...111 1 lsb = v ref /4096 (ad7938) 1 lsb = v ref /1024 (ad7939) 1 lsb +v ref ?1 lsb analog input adc code 0v note: v ref is either v ref or 2 v ref 000...001 000...010 111...110 111...000 011...111 f i gur e 1 6 . ad79 38 /ad7 93 9 idea l t r a n s f e r cha r a c t e r i stic with str a ight bin a r y o u tput c o ding
ad7938/ad7939 rev. 0 | page 18 of 32 03715-0-026 100...000 011...111 1 lsb = 2 v ref /4096 (ad7938) 1 lsb = 2 v ref /1024 (ad7939) ?v ref + 1 lsb v ref +v ref ? 1 lsb adc code 100...001 100...010 011...110 000...001 000...000 111...111 f i gur e 1 7 . ad79 38 /ad7 93 9 idea l t r a n s f e r cha r a c t e r i stic with t w os c o mple ment o u tput coding and 2 v re f ra n g e typical connection diagram f i g u re 1 8 show s a t y pi c a l c o n n e c t i on d i ag r a m f o r t h e ad7938/ad79 39. th e a g nd a nd d g nd p i ns a r e co nn ec t e d t o g e t h er a t t h e de vice fo r g o o d n o is e s u p p r es si o n . th e v refin / v refo ut p i n is deco u p led t o a g nd wi t h a 0.47 f ca p a ci t o r t o a v oi d noi s e pi c k up i f t h e i n te r n a l re f e re nc e i s u s e d . a l te r n a t iv ely , v refin /v refo ut ca n b e co nn e c t e d t o a n exter nal r e fer e n c e s o ur c e , a nd i n t h is ca s e , t h e r e fer e n c e p i n sh o u ld b e de c o u p le d wi t h a 0.1 f ca p a ci t o r . i n b o t h c a s e s, t h e analog in p u t ra n g e can ei t h er be 0 v t o v ref ( r an ge b i t = 0) o r 0 v t o 2 v ref (ran ge b i t = 1). th e a n alo g in p u t co nf igura t io n can b e ei t h er eig h t sin g le - en de d i n p u ts, fo ur dif f er en t i al p a irs, fo ur ps eud o -dif fer e n t i a l p a irs, o r s e v e n p s eudo-dif fer e n t i a l in p u ts (s e e t a b l e 9). the v dd p i n is co nne c t e d t o ei t h er a 3 v o r 5 v s u p p ly . the v o l t a g e ap p l i e d t o t h e v dr iv e in p u t co n t rols t h e v o l t a g e o f t h e dig i t a l in t e r f ace a nd h e r e , i t is co nn e c te d t o t h e s a m e 3 v s u p p ly o f t h e m i c ropro c e ss or to a l l o w a 3 v l o g i c i n te r f a c e ( s e e t h e d i g i t a l inp u t s s e c t i o n ) . 03715-0-027 0.1 f1 0 f 3v/5v supply 3v supply c/ p ad7938/ad7939 0.1 f 0.1 f external v ref 0.47 f internal v ref 0 to v ref / 0 to 2 v ref agnd dgnd w/b clkin cs v drive v in 0 v dd v refin /v refout v in 7 10 f 2.5v v ref rd convst wr busy db0 db11/db9 f i g u re 18. t y pic a l conne c t io n d i ag r a m analog input struc t ure f i g u re 1 9 show s t h e e q u i v a l e n t c i rc u i t of t h e an a l o g i n put s t r u c t ur e o f th e ad7938/ad79 39 in dif f er en t i a l /ps e udo dif f er en t i a l mo de. i n sing le-e nde d m o de, v in? is in t e r n a l ly ti ed t o a g n d . t h e f o ur d i od e s p r o v i d e es d p r o t ecti o n f o r th e a n alog i n p u ts . c a r e m u s t be tak e n t o e n s u r e tha t th e a n alog in p u t sig n als ne v e r exce e d t h e su p p l y ra ils b y m o r e t h a n 300 mv . this c a us es th es e dio d es t o become f o r w a r d-b i as ed and s t a r t s co n d uctin g i n t o t h e s u b s tra t e . t h ese d i od es ca n co n d uct u p t o 10 ma wi t h o u t ca usin g ir r e v e rsi b le da mage t o t h e p a r t . the c1 c a p a ci t ors in f i gur e 19 ar e typ i cal l y 4 pf a nd can p r i m a r i l y b e a t tri b u t ed t o p i n ca pa c i ta n c e . t h e r e s i s t o r s a r e lu m p e d c o m p o n e n t s m a d e up of t h e on re s i st a n c e of t h e swi t ch es. th e va l u e o f th es e r e sis t o r s is typ i cal l y a b o u t 100 ?. the c2 c a p a ci t ors a r e t h e ad c s s a m p li n g c a p a ci t o rs an d ha v e a ca p a c i tan c e o f 4 0 pf typ i cal l y . f o r a c a p pl i c a t i o ns , re mov i ng h i g h f r e q u e nc y c o m p o n e n t s f rom t h e a n alog in p u t sig n al is r e co mmende d b y t h e us e o f a n r c lo w-p a s s f i l t er on t h e r e le v a n t analog in p u t pins. i n a p pli c a t io ns w h er e ha r m oni c dis t o r t i o n and sig n al-t o- n o is e ra t i o a r e cr i t ical, t h e a n alog in p u t s h o u l d b e dr i v en f r o m a lo w i m p e dance s o urce . l a r g e so ur ce im pe d a n c e s s i gn i f ica n tl y a f f e ct th e a c pe rf o r m a n c e o f t h e a d c. thi s ma y ne ces s i t a te t h e us e o f an i n p u t b u f f er am pl i f i e r . t h e c h oi c e of t h e op am p i s a f u nc t i o n of t h e p a r t ic u l a r a p plica t ion. r1 c2 v in + v dd c1 d d 03715-0-028 r1 c2 v in ? v dd c1 d d f i g u re 19. equiv a le nt a n al og input c i rcuit , convers i on p h as e switc h es o p e n , t r ack phas e sw itc h es cl os ed w h en n o am pli f ier is us e d t o dr i v e t h e a n alog in p u t, t h e s o ur ce im p e dan c e sh ou ld b e li mi t e d to lo w val u es. the maxim u m s o ur ce im p e dance dep e n d s on t h e am o u n t o f t h d t h a t can b e t o lera t e d . th e thd i n cr e a s e s as t h e s o ur ce i m p e dan c e i n cr e a s e s a nd p e r f o r ma n c e deg r ades. f i gu r e 20 a nd f i gur e 21 sh o w a g r a p h o f t h e thd vs. s o ur ce i m p e dance wi t h a 50 kh z i n p u t tone for b o t h v dd = 5 v a n d 3 v in sin g l e -en d ed m o de an d d i f f e r e n ti al m o d e , r e s p ecti v e l y .
ad7938/ad7939 rev. 0 | page 19 of 32 r source ( ? ) thd (db) ?40 ?45 ?50 ?55 ?80 ?75 ?70 ?65 ?60 ?90 ?85 10 100 1k 10k 03715-0-018 f in = 50khz v dd = 5v v dd = 3v f i gure 20. thd vs. s o urc e i m p e d a nce in sing le -end ed mode r source ( ? ) thd (db) ?60 ?80 ?75 ?70 ?65 ? 100 ?85 ?90 ?95 10 100 1k 10k 03715-0-019 f in = 50khz v dd = 5v v dd = 3v f i gur e 2 1 . thd vs . s o ur c e im p e da nc e in di ffe r e ntia l mo de f i gur e 22 s h o w s a g r a p h o f t h e thd v s . t h e analog in p u t f r eq uen c y f o r va r i o u s s u p p lies while s a m p ling a t 1.5 m h z wi t h an sclk o f 25.5 mh z. i n t h is cas e , th e s o u r ce im p e dan c e is 10 ?. input frequency (khz) thd (db) ?50 ?60 ?70 ?80 ? 110 ? 100 ?90 ? 120 0 100 400 200 300 600 500 700 03715-0-020 f sample = 1.5msps range = 0 to v ref v dd = 3v single-ended mode v dd = 5v/3v differential mode v dd = 5v single-ended mode f i g u re 22. th d v s . a n al og input f r equ e nc y f o r v a ri ous su p p ly v o lt ag es analog inputs the ad7938/ad7939 ha v e s o f t wa r e s e lec t ab le a n alog in p u t co nf igura t io n s . the us er can cho o s e ei t h er eig h t sin g le-e n d e d in p u ts, fo ur f u l l y dif f er en t i al p a irs, fo ur ps eudo-dif fer e n t ial p a irs, o r s e v e n p s eudo-dif fer e n t i a l in p u ts. th e ana l og in p u t co nf igura t io n is ch os en b y s e t t i n g t h e mo d e 0/ mo d e 1 b i t s i n t h e i n t e r n al con t r o l r e g i s t er (s e e t a b l e 9). single-ended mode the ad7938/ad7939 can ha ve eig h t sin g le-ended a n alog in p u t cha n n e ls b y s e t t in g t h e mo d e 0 a nd mo d e 1 b i ts in t h e con t r o l r e g i s t er t o 0. i n a p plic a t ion s w h er e t h e sig n al s o ur ce has a hig h im p e dan c e , i t is r e co mme n d e d to b u f f er t h e a n a l og in p u t b e fo r e a p ply i n g i t t o t h e ad c. th e analog in p u t ra n g e can b e p r ogra m m e d t o be ei t h er 0 t o v ref o r 0 t o 2 v ref . i f t h e a n alog i n p u t sig n al t o b e s a m p le d is b i p o l a r , t h e in t e r n al r e f e r e n c e o f th e a d c ca n be us ed t o e x t e rn all y b i a s u p th i s s i gn al t o m a k e i t th e co rr ect f o rm a t f o r th e a d c . f i gur e 23 s h o w s a typ i cal co nn e c t i o n dia g ram w h en op era t i n g t h e ad c in si ng le-e n d e d m o de. 0.47 f +1.25v v in r r 3r 0v ?1.25v +2.5v 0v v in0 v in7 v refout ad7938/ ad7939* *additional pins omitted for clarity 03715-0-031 f i gure 23. sing le -ended mod e conn e c t ion d i agr a m differenti a l m o de the ad7938/ad7939 can ha ve f o ur dif f er en tia l a n alog in p u t p a i r s by s e tt i n g t h e m o d e 0 a n d m o d e 1 bit s i n t h e c o n t ro l r e g i s t er t o 0 an d 1, r e s p ec ti v e l y . dif f er en t i al sig n als ha v e s o m e b e n e f i t s o v er sin g le-e n d e d sig n a l s, in cl udi n g n o is e imm u ni ty b a s e d o n t h e de vice s c o m m on - m o d e re j e c t i o n a n d i m prove m e n t s i n d i s t or t i on p e r f o r ma n c e . f i gur e 24 def i n e s t h e f u l l y dif f er en t i al a n alog in p u t o f th e ad7938/ad7939. 03715-0-032 v ref p-p v in+ v in? v ref p-p *additional pins omitted for clarity ad7938/ ad7939* common-mode voltage f i g u re 24. d i f f e r e nt ia l input d e f i nit i on
ad7938/ad7939 rev. 0 | page 20 of 32 the am pli t ude o f t h e dif f er en t i al sig n al is t h e dif f er en ce b e tw e e n t h e sig n als a p plie d t o t h e v in+ and v in? p i n s in eac h dif f er en t i al p a ir (i .e ., v in+ ? v in ? ). v in+ a nd v in ? shou l d b e sim u l t an e o us l y dr i v en b y tw o sig n als e a c h o f a m p l i t ude v ref (o r 2 v ref dep e ndin g o n t h e ran g e c h os en) tha t ar e 180 o u t o f phas e (ass uming t h e 0 t o v ref ra n g e is s e le c t e d ). th e a m pl i t ude o f t h e dif f er en t i al sig n al is t h er e f o r e ?v ref to + v ref peak -t o- p e ak (i . e ., 2 v ref ) . t h i s i s re g a rd l e ss of t h e c o m m o n mo d e (cm). th e comm on m o de is t h e a v era g e o f t h e tw o sig n als, i . e . (v in+ + v in? ) / 2 a nd is t h er efo r e t h e v o l t a g e on w h ich t h e tw o in p u ts a r e ce n t e r e d . this r e s u l t s in t h e s p an o f e a ch i n p u t b e i n g cm v ref /2. this v o l t a g e has to b e s et u p ext e r n al ly a n d i t s ra n g e va r i es w i t h t h e r e fer e n c e val u e v ref . a s t h e val u e o f v ref in cr e a s e s, t h e comm on- m o d e ran g e de cr e a s e s. w h en dr i v i n g t h e i n p u ts wi t h a n am plif ier , t h e ac t u al comm o n -mo d e ra n g e is det e r m i n e d b y t h e am plif ier s ou t p ut v o l t a g e s w i n g. f i gur e 25 a nd f i gur e 26 s h o w ho w th e co mm on-m o d e ra n g e typ i cal l y va r i es wi t h v ref f o r a 5 v p o w e r s u p p l y usin g th e 0 t o v ref ra n g e o r 2 v ref ra n g e , r e s p ecti v e l y . t h e co m m o n m o de m u s t be in th i s ra n g e t o g u a r a n t e e t h e fun c ti o n ali t y o f th e ad7938/ad79 39. w h en a con v ersio n t a k e s pl ace , t h e comm o n mo de is r e je c t e d , r e su l t in g i n a vi r t ua l l y n o is e f r e e sig n a l o f a m pl i t ud e ?v ref to +v ref co r r es p o n d in g t o t h e dig i tal co des o f 0 t o 4096 f o r th e ad7938 an d 0 to 1024 f o r th e ad7939. i f th e 2 v ref ra n g e is us e d t h en t h e i n p u t sig n al am pli t ude w o u l d ext e nd f r o m ?2v ref to + 2 v ref af te r c o n v e r s i on . v ref (v) common-mode range (v ) 3.5 3.0 2.0 1.5 2.5 1.0 0.5 0 0 0.5 1.5 1.0 2.0 2.5 3.0 03715-0-033 t a = 25 c f i gure 25. input common-m ode r a ng e vs . v ref (0 t o v ref ra nge , v dd = 5 v ) v ref (v) common-mode range (v ) 4.5 4.0 3.0 1.5 2.0 2.5 3.5 1.0 0.5 0 0.1 0.6 1.6 1.1 2.1 2.6 03715-0-034 t a = 25 c f i gure 26. input common-m ode r a ng e vs . v ref (2 v ref ra nge , v dd = 5 v ) driving differential inputs dif f er en t i al op e r a t io n r e q u ir es t h a t v in + an d v in ? be sim u l t an eo us l y dr i v en wi t h tw o eq ual sig n als tha t a r e 180 o u t o f phas e . th e comm on m o de m u s t b e s et u p exter nal l y a n d has a ra n g e tha t i s de t e rm in ed b y v ref , t h e p o w e r s u p p l y , a n d t h e p a r t ic u l a r a m pli f ier us e d t o dr i v e t h e a n alog in pu ts. dif f er en t i al m o de s o f o p era t io n wi t h ei t h er a n ac o r dc i n p u t p r o v ide t h e b e st t h d p e r f or m a nc e ove r a w i d e f r e q u e nc y r a nge. si nc e not all a p p l i c a t i o n s h a v e a s i g n al p r eco n d i ti o n ed f o r d i f f e r e n ti al o p er a t ion, t h er e is o f ten a ne e d to p e r f o r m sin g le-ende d-to - dif f er en t i al co n v ersio n . using an op a m p p a ir an o p a m p p a ir ca n be us e d t o dir e c t l y co u p le a dif f er en t i al sig n al t o o n e o f th e a n alog in p u t p a irs o f th e ad7938/ad7939. the cir c ui t conf igur a t io n s sh ow n in f i gur e 27 and f i gur e 28 sh o w h o w a d u a l o p a m p can b e us e d to con v er t a sin g le-e nde d sig n al in t o a dif f er en t i a l sig n al fo r b o t h a b i p o lar a n d u n i p ola r i n p u t s i gn al , r e s p ecti v e l y . the v o l t a g e a p plie d t o p o i n t a s ets u p t h e co mm on- m o d e vol t a g e. i n b o t h di a g r a m s , i t is c o nn e c te d in s o m e wa y to t h e r e fer e n c e , b u t an y val u e i n t h e co mm o n - m o d e ra n g e can b e in p u t her e t o s e t u p th e co mm o n m o de . a s u i t ab le d u al o p a m p t h a t co u l d b e us e d i n t h is co nf ig ur a t io n to p r o v i d e dif f er en t i a l dr i v e t o the ad7938/ad7939 is th e ad8022. t a k e ca r e w h en ch o o sin g t h e o p a m p; t h e s e le c t i o n dep e nds o n t h e r e q u ir e d p o w e r s u p p ly a nd sys t em p e r f o r m a n c e ob je c t i v es. the dr i v er cir c ui ts i n f i gur e 27 a nd f i gur e 28 ar e o p t i mi ze d fo r d c c o upl i ng a p p l i c a t i o ns re qu i r i n g b e st d i s t or t i on p e r f or m a nc e . the cir c ui t conf igura t io n s h ow n in f i gur e 27 co n v er ts a uni p ol a r , sin g le- e n d e d sig n al in to a dif f er en t i al sig n al. the dif f er en t i al o p a m p dr i v er c i r c ui t in f i gur e 28 is co nf igur e d to c o n v e r t a n d l e vel sh i f t a s i ng l e - e nd e d , g rou n d - re f e re nc e d (b i p ola r ) sig n al t o a dif f er en t i al sig n al cen ter e d a t t h e v ref leve l o f t h e a d c.
ad7938/ad7939 rev. 0 | page 21 of 32 220 ? 10k ? 2 v ref p-p v ref gnd 390 ? 220 ? 220 ? 20k ? 220 ? 27 ? 27 ? v+ v? v+ v? a v in+ v in? v ref ad7938/ ad7939 0.47 f 03715-0-035 3.75v 2.5v 1.25v 3.75v 2.5v 1.25v f i gure 2 7 . dua l o p a m p cir c ui t to co nv er t a single-ended uni p ol ar si gnal i n to a di ffer e nt i a l si g n a l 10k ? 2 v ref p-p v ref gnd 390 ? 220 ? 220 ? 20k ? 220 ? 27 ? 27 ? v+ v? v+ v? a v in+ v in ? v ref ad7938/ ad7939 0.47 f 03715-0-036 3.75v 2.5v 1.25v 3.75v 2.5v 1.25v f i gure 2 8 . dua l o p a m p cir c ui t to co nv er t a single-ended bipo l a r s i g n a l int o a d i f f e r e nt ia l u n ipol ar sig n al pseudo -differential mode the ad7938/ad7939 can ha ve f o ur ps eudo-dif f e r e n t ial p a irs ( p s e udo m o de 1) o r s e ven ps eu do dif f er en t i a l i n p u ts ( p s e udo m o de 2) b y s e t t in g th e m o d e 0 a nd m o d e 1 b i ts in t h e con t r o l r e g i s t er t o 1, 0 a nd 1, 1, r e s p ec tiv e l y . i n t h e c a s e o f th e f o ur ps eudo-dif fer e n t ia l p a irs, v in + i s c o n n e ct ed t o th e s i g n a l s o u r c e whic h m u s t ha ve a n am p l i t ude o f v ref (o r 2 v ref dep e n d i n g o n t h e ra n g e chos en) t o ma k e us e o f t h e f u l l d y na mic ra n g e o f t h e p a r t . a dc in p u t is a pplie d t o t h e v in ? p i n. the v o l t a g e a p pl i e d to t h i s i n put prov i d e s a n of f s e t f rom g rou nd or a p s e u d o g rou nd f o r t h e v in+ i n p u t. i n t h e cas e o f t h e s e ven ps eudo- dif f er en t i al in puts, t h e s e v e n a n a l og in p u t sig n al s in p u ts a r e r e fer r e d to a dc vol t a g e a p plie d to v in 7. th e b e n e f i t o f ps eudo- dif f er en t i al in puts is t h a t t h e y s e p a ra t e t h e a n alog in p u t sig n al g rou nd f rom t h e a d c s g rou n d a l l o w i ng d c c o m m o n - m o d e volt age s to b e c a nc el l e d. t y pi c a l l y , t h i s r a nge c a n e x te nd to ?0.3 v t o +0.7 v w h en v dd = 3 v o r ?0.3 v t o +1.8 v when v dd = 5 v . f i g u re 2 9 show s a c o n n e c t i on d i ag r a m f o r p s e u d o - dif f er en t i al mo de . v in+ v in ? v ref ad7938/ ad7939* *additional pins omitted for clarity 03715-0-037 v ref p-p 0.47 f dc input voltage f i g u re 29. p s eud o -d if f e r e nt ia l m o de conne c t io n d i ag r a m analog input selection a s sh o w n i n t a b l e 9, t h e us er c a n s et u p t h e i r analog in p u t co nf igura t io n b y s e t t in g t h e va lues in t h e mo d e 0 a nd mo d e 1 b i ts in t h e co n t rol r e g i s t er . a s s u min g t h e co nf ig ura t io n has b e e n ch os en, t h er e a r e dif f er en t w a ys o f s e le c t in g t h e a n alog in p u t t o b e con v er te d de p e ndi n g o n t h e st a t e o f t h e s e q a nd s h d w b i t s i n t h e c o n t ro l re g i ste r . traditional m u ltichannel operation (seq = sh dw = 0) an y o n e o f eig h t a n alog in p u t cha n n e ls o r fo ur p a irs o f cha nne ls ma y b e s e le c t e d fo r co n v ersio n in an y o r d er b y s e t t i n g t h e s e q an d sh dw bit s i n t h e c o n t ro l re g i ste r to 0 . t h e ch an nel to b e co n v er t e d is s e l e c t e d b y wr i t ing t o t h e addr es s b i ts, ad d2 t o ad d0, in t h e c o n t r o l r e g i s t er to p r og ra m t h e m u l t i p lexer p r io r t o t h e con v ersion. this m o d e o f o p era t ion is t h a t o f a t r adi t iona l m u l t icha nne l a d c w h er e e a ch da t a wr i te s e le c t s t h e n e xt ch an nel f o r c o n v e r s i on . f i g u re 3 0 show s a f l ow ch ar t of t h i s m o d e o f o p er a t i o n. t h e channel co nf igur a t io n s a r e sh own i n t a b l e 9. power on write to the control register to set up operating mode, analog input and output configuration set seq = shdw = 0. select the desired channel to convert (add2 to add0). issue convst pulse to initiate a conversion on the selected channel. initiate a read cycle to read the data from the selected channel. initiate a write cycle to select the next channel to be converted by changing the values of bits add2 to add0 in the control register. seq = shdw = 0. 03715-0-038 f i g u re 30. t r adit io n a l m u lt i c ha nne l o p er at ion f l o w ch a r t using the sequ e n c e r: progra mmab le sequ e n c e (seq = 0, shdw = 1 ) the ad7938/ad7939 ma y be c o nf igur ed t o a u to ma tic a l l y c y c l e th r o u gh a n u m b e r o f se lect ed c h a n n e ls us i n g th e o n - c h i p p r ogra m m a b l e seq u en cer b y set t in g s e q = 0 a n d s h d w = 1 in t h e con t r o l r e g i s t er . the a n alog in p u t cha n n e ls t o b e con v er t e d a r e s e le c t e d b y s e t t i n g t h e r e le v a n t b i t s in t h e s h ado w r e g i s t er t o 1, s e e t a b l e 11.
ad7938/ad7939 rev. 0 | page 22 of 32 on ce t h e s h adow r e g i s t er has b e en p r og ra mm e d w i t h t h e r e q u ir e d s e q u ence , t h e n e xt con v ersio n exe c u t e d is o n t h e lo w e s t cha nne l p r og ra mm e d in t h e shd w r e g i s t er . the n e xt co n v ersio n exe c u t e d is on t h e next hig h e s t channe l i n t h e seq u en ce a n d s o o n . w h en t h e la s t c h a n n e l i n t h e s e q u en ce i s co n v er t e d , t h e i n t e r n al m u l t i p le xer r e t u r n s t o th e f i rs t cha n n e l se lect e d in th e s h a d o w r e gi s t e r a n d co mm en ces th e s e q u en ce ag ai n . i t is n o t n e ces s ar y t o wr i t e t o t h e co n t r o l r e g i s t e r a g a i n on ce a seq u en ce r o p e r a t i o n ha s been in i t i a t e d . th e wr in p u t m u st b e k e pt hig h t o en sur e t h a t t h e co n t r o l r e g i s t er is no t accide n t al ly ove r w r itte n or t h a t a s e qu e n c e op e r a t i o n i s not i n te r r upte d. i f th e co n t r o l r e g i s t er is wr i t t e n t o a t an y tim e d u r i n g th e s e q u e n ce , t h en en s u r e t h a t t h e s e q a nd s h d w b i ts a r e s et t o 1, 0 t o a v o i d i n t e r r u p t i n g t h e co n v ersio n s e q u en c e . th e s e q u e n ce p r o g r a m r e ma i n s i n fo r c e un t i l such t i me as t h e ad7938/ad79 39 is wr i t t e n t o a nd t h e s e q and s h d w b i ts a r e co nf igur ed wi t h an y b i t com b ina t ion excep t 1, 0. f i gur e 31 s h o w s a f l o w cha r t o f t h e p r og ra mma b l e s e q u e n ce op era t ion. power on write to the control register to set up operating mode, analog input and output configuration set seq = 0 shdw = 1. initiate a write cycle. this write cycle is to the shadow register. set relevant bits to select the channels to be included in the sequence. seq bit = 1 shdw bit = 0 continuously convert consecutive channels selected with each convst pulse but allows the range, coding, analog input type, etc bits in the control register to be changed without interrupting the sequence. continuously convert consecutive channels selected in the shadow register with each convst pulse. 03715-0-039 wr = high seq bit = 0 shdw bit = 1 f i gure 31. p r ogr a m m ab le s e qu ence f l o w ch a r t consecuti v e s e que n c e (seq = 1, shdw = 1 ) a s e q u en ce o f c o n s ec u t i v e c h a n n e ls ca n be co n v er t e d b e g i nning wi t h chann e l 0 a nd en din g wi t h a f i nal c h ann e l s e lec t e d b y wr i t i n g t o t h e a d d2 t o ad d0 b i ts in t h e co n t rol r e g i s t er . this is do ne b y s e t t i n g t h e s e q an d s h d w b i ts i n t h e con t r o l r e g i s t er t o 1. i n t h is m o de , t h e s e q u encer can b e us e d w i t h o u t ha vin g t o wr i te t o t h e s h ado w r e g i s t er . once t h e co n t r o l r e g i s t e r is wr i t t e n t o , t o s et t h is m o de up , t h e n e xt con v ersio n is o n cha n n e l 0, t h en cha n n e l 1, and s o o n un til t h e cha n n e l s e lec t e d b y t h e addr es s b i ts (ad d 2 t o a d d0) is r e ach e d . th e c y cle be gin s a g a i n p r o v i d ed t h e wr i n p u t i s ti ed h i gh . i f lo w , th e s e q a nd s h d w b i t s m u s t b e s et t o 1, 0 t o al lo w t h e ad c t o co n t in ue i t s p r ep r o g r a m m e d s e q u en c e unin t e r r u p t e d . f i gur e 32 s h o w s t h e f l o w cha r t o f t h e co ns e c u t i v e s e q u e n ce mo de . power on write to the control register to set up operating mode, analog input and output configuration select final channel (add2 to add0) in consecutive sequence. set seq = 1 shdw = 1. continuously convert a consecutive sequence of channels from channel 0 up to and including the previously selected final channel on add2 to add0 with each convst pulse. seq bit = 1 shdw bit = 0 continuously convert consecutive channels selected with each convst pulse but allows the range, coding, analog input type, etc bits in the control register to be changed without interrupting the sequence. 03715-0-040 f i gure 32. cons ecu tive s e qu ence m o d e f l o w ch a r t reference section the ad7938/ad7939 can o p er a t e wi th ei t h er th e on-c hi p o r e x te r n a l re f e re nc e. t h e i n te r n a l re f e re nc e i s s e l e c t e d by s e tt i n g t h e ref b i t in t h e i n t e r n al con t r o l r e g i s t er t o 1. a b l o c k di a g ram of t h e i n te r n a l re f e re nc e c i rc u i t r y i s show n i n fi g u re 3 3 . t h e i n te r n a l re f e re n c e c i rc u i t r y i n clu d e s an on - c h i p 2 . 5 v b a nd g a p r e fer e n c e an d a r e fer e n c e b u f f er . w h e n usin g t h e in ter nal re f e re nc e, t h e v refin /v refo ut p i n s h o u ld be decou p led t o a g nd wi t h a 0.47 f c a p a ci t o r . this in t e r n al r e f e r e n c e n o t onl y p r o v ides t h e r e fer e n c e fo r t h e analog-t o-dig i t a l co n v ersio n , b u t i t can als o b e us e d ext e r n al ly in t h e sys tem. i t is r e co mme n d e d t h a t t h e r e fer e nce o u t p u t is b u f f er e d usin g a n ex t e r n al p r e c isio n op am p b e f ore apply i ng it a n y w he re i n t h e s y ste m . reference ad7938/ ad7939 adc buffer 03715-0-041 v refin / v refout f i gure 33. inte rn al r e fer e n c e c i rcuit bl ock d i agr a m a l te r n a t iv ely , an e x te r n a l re fe renc e c a n b e a p pl i e d to t h e v refin / v refo ut p i n o f th e ad7938 /ad7939. an ext e r n al r e f e r e n c e in p u t is s e le c t e d b y s e t t in g t h e ref b i t in t h e i n t e r n a l co n t r o l r e g i st er t o 0. th e ext e r n al r e fer e n c e i n pu t ra n g e is 0.1 v t o v dd . i t i s im p o r t an t t o ens u r e t h a t , w h e n ch o o sin g t h e r e fer e n c e v a l u e , t h e max i m u m a n a l o g in p u t r a n g e ( v in ma x ) i s n e v e r gr ea t e r th a n v dd + 0. 3 v t o co m p l y wi th t h e m a xi m u m ra tin g s o f th e d e v i ce . f o r exa m ple , if o p era t i n g i n dif f er en t i al m o de a nd t h e r e fer e n c e i s s o u r c e d f rom v dd , th en t h e 0 t o 2 v ref ra n g e ca nn o t b e us e d . this is b e ca us e t h e analog in p u t sig n al ran g e w o u l d n o w e x te nd to 2 v dd , wh i c h w o uld e x ceed th e m a xi m u m ra tin g co ndi t i on s. i n t h e ps eudo- d if fer e n t ial mo des, t h e us er m u st en s u r e t h a t v ref + (v in? ) v dd w h en usin g t h e 0 t o v ref ra n g e , o r wh en usin g t h e 2 v ref ra n g e tha t 2 v ref +(v in? ) v dd .
ad7938/ad7939 rev. 0 | page 23 of 32 i n a l l c a s e s, t h e sp e c if ie d r e fer e n c e is 2.5 v . the p e r f o r ma nce o f t h e p a r t w i t h dif f er en t r e fe r e n c e va l u es is s h own i n f i gur e 9 t o f i gur e 11. the val u e o f t h e r e fer e n c e s ets t h e a n alog in p u t s p a n and t h e c o mm on- m o d e v o l t a g e ra n g e . e r ror s i n t h e re f e re nc e s o u r c e re su lt i n g a i n e r ror s i n t h e ad7938/ad79 39 tra n sf er f u n c tio n and add t o s p ecif ie d f u l l - s c ale er r o r s o n t h e p a r t . t a b l e 12 lis t s ex a m ples o f s u i t able v o l t a g e r e fer e n c es t h a t co u l d b e u s e d t h a t are a v ai l a bl e f rom a n a l o g d e v i c e s an d f i g u re 3 4 sh o w s a ty p i ca l co nne c t io n di a g r a m fo r a n ex ter n a l r e fer e n c e. table 12. e x am ples of suit able voltage re fere nces reference ou tpu t voltage initial accu racy (% max) operating current (a) ad780 2.5/3 0.04 1000 a d r 4 2 1 2 . 5 0 . 0 4 5 0 0 a d r 4 2 0 2 . 0 4 8 0 . 0 5 5 0 0 03715-0-042 1 ad780 nc 8 2 +v in nc 7 3 gnd 6 4 temp 5 o/pselect trim v out v ref 2.5v nc nc v dd nc = no connect 10nf 0.1 f 0.1 f 0.1 f *additional pins omitted for clarity ad7938/ ad7939* f i g u re 34. t y pic a l v ref c o nnec t ion d i agr a m digital inputs the dig i tal in p u ts a p p l ie d t o t h e ad7938/ad79 39 a r e n o t limi te d b y t h e maxim u m ra t i ngs t h a t limi t t h e a n alog in p u ts. i n s t e a d , t h e dig i t a l in pu ts a p plie d can g o t o 7 v a nd a r e n o t r e s t ri ct ed b y th e a v dd + 0.3 v limi t as o n t h e a n alog in p u ts. an o t h e r ad v a n t a g e o f t h e dig i t a l in p u ts n o t b e i n g r e s t r i c t e d b y th e a v dd + 0.3 v limi t is t h e fac t t h a t p o w e r s u p p ly s e q u en c i n g is s u es a r e a v o i de d . i f an y o f t h e s e in p u ts a r e a pplie d b e fo r e av dd , t h e n t h er e is n o r i s k o f l a t c h-u p as t h er e w o u l d b e on t h e a n a l og in p u t s if a sig n a l g r e a t e r t h a n 0.3 v w a s a p plie d p r io r t o av dd . v drive input the ad7938/ad7939 ha v e a v dr iv e fe a t ur e. v dr iv e co n t r o ls th e v o l t a g e a t w h ich t h e p a ral l e l i n t e r f ace o p era t es. v dr iv e allo w s th e a d c to e a s i ly i n te r f ac e to 3 v and 5 v pro c e s s o rs . f o r exa m p l e , if th e ad7938 /ad7939 a r e o p era t ed wi t h a n a v dd o f 5 v a n d t h e v dr iv e pi n i s p o we re d f rom a 3 v supply , t h e ad7938/ad79 39 ha v e bet t er dyna mic p e r f o r ma nce wi t h a n av dd o f 5v whi l e s t il l bein g ab le t o in ter face dir e c t l y t o 3 v pro c e s s o r s . c a re shou l d b e t a ke n to e n su re v dr i v e do es n o t e x ceed a v dd b y m o r e th a n 0. 3 v (see th e a b so l u t e m a xim u m ra t i n g s s e c t i o n ) .
ad7938/ad7939 rev. 0 | page 24 of 32 parallel interf ace the ad7938/ad7939 ha v e a f l exi b le , hig h s p e e d , p a ral l e l in t e r f ace . this in t e r f ace is 12-b i ts (ad7938) o r 10-b i ts (ad7939) wide a nd is c a p a b l e of o p era t in g in ei th er w o r d (w / b ti ed hi gh ) o r b y t e (w / b ti ed lo w ) m o d e . th e co n v s t sig n al is us ed t o ini t ia t e co n v er s i o n s an d w h en o p era t in g in a u to s h utdow n or a u to st andb y mo d e , i t i s u s e d to i n i t i a te po w e r u p . a fa l l in g e d ge on t h e co n v s t sig n al is u s ed t o ini t ia t e co n v ersio n s and i t als o p u ts t h e ad c t r ack-and-h o ld in t o t r ack. on ce t h e co n v s t sig n al g o es lo w , th e b u s y sig n al go es hig h fo r t h e d u ra t i o n o f t h e con v ersio n . i n b e tw e e n co n v ersio n s, co n v s t m u st b e brou g h t h i g h f o r a m i n i m u m t i me of t 1 . t h i s m u s t ha p p e n a f ter t h e 14 th fal l ing edg e o f clki n; o t h e r w is e , t h e co n v ersio n is ab o r te d an d t h e t r ack-and- h o ld go es b a ck i n to t r ack. a t t h e e nd o f t h e con v ers i o n , b u s y g o es lo w a n d can b e us e d t o ac t i v a te a n i n t e r r u p t s e r v ice r o u t i ne . the cs a nd rd lin e s a r e t h en ac ti va t e d in p a ral l e l t o r e ad t h e 12 - o r 10- b i ts o f co n v ersio n da t a . w h e n p o w e r su p p lies a r e f i rs t a p plie d t o t h e de vice, a r i sin g e d ge o n co n v s t is ne ce s s a r y t o p u t t h e t r ack- a nd-h o ld in t o tr ac k. th e ac q u isi t io n tim e o f 125 n s minim u m mu s t b e a l l o w e d b e f o r e co n v s t is b r o u g h t lo w t o ini t i a t e a co n v ersio n . the ad c t h e n g o es in t o h o ld o n t h e fal l in g e d ge o f co n v s t a nd back in t o t r ac k o n t h e 13 th r i sin g edg e o f clkin a f t e r th i s (see f i g u r e 35). w h e n o p e r a t in g th e devi ce in a u t o sh u t down or a u t o s t and b y m o de , w h er e t h e ad c p o w e rs d o w n a t t h e en d o f ea c h co n v e r s i o n , a ri s i n g ed g e o n t h e co n v s t sig n al is us ed to p o w e r u p th e de vice . t 2 t 3 t 20 t 14 t 11 t 9 t 13 t 12 t 10 t convert t aquisition t quiet t 1 12 3 4 5 1 2 1 3 1 4 b a data data old data db0 to db11 db0 to db11 rd cs internal track/hold busy clkin convst three-state three-state with cs and rd tied low 03715-0-004 f i gur e 3 5 . ad79 38 /ad7 93 9 p a r a l l e l inte r f a c e co n v e r s i on a n d re a d c y c l e in w o r d m o de ( w / b = 1)
ad7938/ad7939 rev. 0 | page 25 of 32 reading data from the a d 7 938/ad7939 w i th th e w / b p i n tie d log i c hig h , th e ad7938 /ad7939 in t e r f ace op era tes in w o r d m o de . i n t h is c a s e , a sin g le r e ad o p era t ion f r o m t h e de vice access es t h e con v ersio n da t a -w o r d on p i n s d b 0/d b 2 to d b 11. th e db8/hb e n p i n as s u m e s i t s d b 8 fu n c t i o n . w i th th e w / b p i n tied to log i c l o w , th e ad7938/ ad7939 in t e r f ace o p era t es in b y t e mo de . i n this cas e , t h e d b 8/hb e n p i n as s u m e s i t s hben f u n c t i on. c o n v ersio n da t a f r o m th e ad79 38/ ad7939 m u s t b e access ed in tw o r e ad o p e r a t i o n s wi th 8 b i t s o f da ta p r o v i d ed o n d b 0 t o d b 7 f o r ea c h o f t h e r e ad o p era t io n s . the hben p i n det e r m i n es w h et her t h e r e ad o p era t io n acces s es t h e hig h b y t e o r t h e lo w b y t e o f t h e 12-o r 10-b i t w o r d . f o r a lo w b y t e r e ad , d b 0 t o d b 7 p r o v ide the eig h t l s bs o f t h e 12-b i t w o rd . f o r 10-b i t o p era t io n, t h e tw o l s b s of t h e l o w by t e a r e 0 s a n d a r e f o l l ow e d by s i x bit s of c o n v e r s i on d a t a . f o r a h i g h by te re a d , db 0 to db 3 prov i d e t h e f o ur ms bs o f th e 12-/10-b i t w o rd . d b 5 t o d b 7 o f th e hig h b y t e prov i d e t h e c h a n n e l i d . f i g u re 3 5 show s t h e re a d c y cl e t i m i ng di a g ra m fo r a 1 2 -/10- b i t t r a n sfer . w h en op era t e d i n w o r d m o de , t h e h b en in put do es n o t exis t, a nd o n ly t h e f i rs t r e ad o p era t ion is r e q u ir ed t o ac ces s da t a f r o m t h e de vice . w h en o p era t e d in by te m o d e , t h e t w o re a d c y cl e s show n i n f i g u re 3 6 are re qu i r e d to a c c e ss t h e f u l l d a t a - w ord f rom t h e d e v i c e . the cs and rd sig n a l s a r e ga te d i n ter n a l ly a n d l e vel t r ig ger e d ac ti v e lo w . i n ei t h er w o r d m o de o r b y t e m o de , cs a nd rd ma y be tied t o g e t h e r a s th e t i m i n g s p eci f i c a t i o n s f o r t 10 a nd t 11 are 0 n s mini m u m. this w o u l d m e an t h e b u s w o u l d b e co nst a n t ly dr i v en b y the ad7938/ad7939. t h e d a t a i s p l aced o n t o th e da t a b u s a tim e t 13 af te r b o t h cs an d rd g o lo w . th e rd ri s i n g ed g e ca n be used t o la t c h da ta o u t o f th e de v i ce . a f t e r a tim e , t 14 , th e da ta lin e s be co m e th r e e - s t a t ed . a l te r n a t iv ely , cs a nd rd ca n be ti e d pe rm a n en tl y lo w a n d t h e c o n v e r s i o n d a ta i s v a l i d a n d p l a c e d o n t o t h e d a ta b u s a ti m e , t 9 , b e f ore t h e f a l l i n g e d ge of b u s y . no t e t h a t i f rd i s p u lsed d u ri n g t h e co n v e r s i o n tim e t h en th i s ca us es a deg r a d a t io n in li n e a r i t y p e r f o r ma n c e o f a p p r o x ima t e l y 0.25 ls b . readin g d u r i n g con v ersio n b y wa y o f tyin g cs a nd rd lo w do es n o t ca us e a n y deg r ada t io n. t 11 t 10 t 13 t 15 t 15 t 16 t 16 t 14 t 12 t 17 low byte high byte db0 to db7 hben/db8 rd cs 03715-0-005 f i gur e 3 6 . ad79 38 /ad7 93 9 p a r a l l e l inte r f a c erea d c y c l e ti mi ng for byte m o de ope r a t i o n ( w / b = 0)
ad7938/ad7939 rev. 0 | page 26 of 32 writing data to the a d 7938/ad7939 wi t h w / b t i e d log i c hig h , a sing le wr i te o p er a t ion t r a n sfers t h e f u l l d a t a - w ord o n db 0 to db 1 1 to t h e c o n t ro l re g i ste r on t h e ad7938/ad79 39. th e d b 8 / hb en p i n as s u mes i t s d b 8 f u n c tion. da t a wr i t t e n t o the ad7938/ad7939 s h o u ld be p r o v i d ed o n t h e d b 0 t o d b 11 i n p u t s wi th d b 0 be in g th e l s b o f th e da ta- w o r d . w i t h w/ b tied log i c lo w , th e ad7938/ad7939 r e q u ir es tw o wr i t e o p era t ion s to t r a n sfer a f u l l 12-b i t w o r d . d b 8/hb e n assum e s i t s h b en f u n c t i on. da t a wr i t t e n t o t h e ad7938/ad79 39 s h o u ld be p r o v ided on t h e db0 t o d b 7 in p u ts. hb e n det e r m i n es w h et h e r t h e b y t e wr i t t e n is hig h b y t e o r lo w b y te da t a . th e lo w b y te of t h e da t a -w o r d sh o u ld b e wr i t t e n f i rs t wi t h d b 0 b e in g t h e ls b o f t h e f u l l da t a -w o r d . f o r t h e hig h b y te w r i t e , hb e n sh ou ld b e hig h and t h e da t a on t h e d b 0 in p u t sh o u ld be da t a b i t 8 o f th e 12-b i t w o r d . i n bo th w o rd a nd b y t e m o de , a sin g le wr i t e op era t ion t o t h e s h ado w r e g i s t er is alwa ys s u f f i cien t sin c e i t is only 8-b i ts wide . f i gur e 37 s h o w s t h e wr i t e c y cle t i min g dia g ram o f t h e ad7938/ad79 39. w h en o p er a t ed in w o r d mo de , th e hb e n in p u t do es n o t e x is t a nd o n ly one wr i te o p er a t ion is r e q u ir e d t o w r ite t h e word of d a t a to t h e d e v i c e . d a t a s h o u l d b e prov i d e d o n d b 0 t o d b 1 1 . w h e n o p er a t e d i n b y t e m o de, t h e tw o wr i te c y cles s h o w n i n f i gur e 38 a r e r e q u ir e d t o wr i t e t h e f u l l da t a - w o r d t o the ad7938/ad7939. i n f i gur e 38, th e f i rs t wr i te t r a n sfers t h e lo w e r eig h t b i ts o f t h e da t a -w o r d f r o m d b 0 t o d b 7, a n d t h e s e co nd w r i t e tr a n s f e r s th e u p pe r f o u r b i t s o f th e d a ta - w o r d . w h e n w r i t i n g t o th e a d 7 9 3 8 / a d 79 39 , th e t o p f o u r b i t s i n t h e hig h b y te m u s t b e 0s. the da t a is l a t c h e d in t o the device o n t h e r i sin g edg e o f wr . t h e d a t a n eeds t o be set u p a tim e , t 7 , b e f ore t h e wr ri s i n g ed g e a nd h e ld fo r a t i m e , t 8 , a f ter t h e wr ri s i n g ed g e . th e cs a nd wr sig n als a r e ga t e d in t e r n al l y . cs a nd wr m a y be ti e d t o g e th e r a s th e tim i n g s p ecif i c a t i o n s f o r t 4 and t 5 are 0 ns m i n i m u m ( a ssu mi ng cs and rd ha v e n o t alr e ady b e en t i e d t o g e t h er). t 8 t 5 t 7 t 6 t 4 data db0 to db11 wr cs 03715-0-002 f i g u re 37. a d 7 9 3 8 / a d79 3 9 p a r a lle l i n t e r f ace w r it e c y c l e tim i ng f o r w o r d m o de o p er at io n ( w / b = 1) t 5 t 4 t 7 t 18 t 18 t 19 t 19 t 8 t 6 t 17 low byte high byte db0 to db11 hben/db8 wr cs 03715-0-003 f i g u re 38. a d 7 9 3 8 / a d79 3 9 p a r a lle l i n t e r f ace w r it e c y c l e tim i ng f o r b y t e m o de o p er at io n ( w / b = 0)
ad7938/ad7939 rev. 0 | page 27 of 32 power modes of operation the ad7938/ad7939 ha v e f o u r dif f er en t p o w e r m o des o f o p era t ion. th es e m o des a r e des i g n e d t o p r o v ide f l exi b le p o w e r ma na g e m e n t o p t i o n s. dif f er en t o p t i o n s can b e ch os en t o o p tim i ze t h e po w e r d i s s i p a t io n/th r o u gh p u t ra t e ra tio f o r dif f er in g a p plic a t io n s . the m o d e o f o p era t io n is s e le c t e d b y t h e p o w e r ma na ge m e n t b i t s, pm1 a nd pm0, in t h e co n t r o l r e g i ster , as det a i l e d i n t a b l e 8. w h en p o w e r is f i rs t a p pli e d t o t h e ad7938/ad79 39 a n o n -c hi p , p o w e r - o n r e s et cir c ui t en s u r e s t h a t t h e def a u l t p o w e r - u p con d i t io n is n o r m al m o de . n o te t h a t , af te r p o we r - on, t h e t r ack- and- hol d i s i n hol d mo d e a nd t h e f i rs t r i sin g e d g e o f co n v s t places t h e t r ack-and - h o ld in t o t r ack mo de. normal mode (pm1 = pm0 = 0) this m o de is in t e nde d fo r t h e f a s t est t h r o u g h pu t ra t e p e r f o r ma n c e b e ca us e t h e us er do es n o t ha v e t o w o r r y a b o u t an y p o w e r - u p tim e s as s o cia t e d wi th t h e ad7938/ad79 39 b e c a u s e it re m a i n s f u l l y p o we re d up at a l l t i me s . a t p o we r - on r e s et, t h is m o de is t h e def a u l t s e t t in g in t h e con t r o l r e g i s t er . autoshutdown (pm1 = 0; p m 0 = 1) i n this m o de o f o p era t ion, th e ad7938/ad7939 a u t o ma tical l y en t e r f u l l s h u t do wn a t t h e e n d o f e a ch co n v ersio n , w h ich is sh own a t p o i n t a in f i gur e 35 and f i gur e 39. i n sh u t do wn mo d e , a l l i n te r n a l c i rc u i t r y on t h e d e v i c e i s p o we re d d o w n . the p a r t s r e t a in info r m a t io n i n t h e con t r o l r e g i st er d u r i n g s h u t do wn. th e t r ac k-and-h o ld a l s o g o es in t o h o ld a t this p o in t a nd r e ma i n s in h o ld as lo ng as t h e d e vice is in sh u t down. t h e ad7938/ad79 39 r e ma in s in sh u t down m o de un til t h e n e xt ri s i n g ed g e o f co n v s t (s e e p o in t b in f i gur e 35 o r f i gur e 39). i n o r d er t o k e ep th e de vice in sh u t do wn f o r as lo n g as p o s s ib le , co n v s t s h o u ld idle lo w betw een con v e r sio n s as sh o w n in f i gur e 39. on this r i sin g edg e , t h e p a r t beg i ns to p o w e r - u p a n d th e tra c k - a n d - h o ld r e t u rn s t o tra c k m o d e . th e po w e r - u p tim e re qu i r e d i s 1 0 ms m i n i m u m re g a rd l e ss of w h e t he r t h e u s e r i s op e r a t i n g w i t h t h e i n te r n a l or e x te r n a l re f e re nc e. t h e u s e r shou l d e n su re t h a t t h e p o we r - up t i m e h a s e l a p s e d b e f o re ini t i a t i n g a con v ersio n . autostandby ( p m1 = 1; pm0 = 0) i n this m o de o f o p era t ion, th e ad7938/ad7939 a u t o ma tical l y e n t e r s t a n d b y m o d e a t th e en d o f ea c h co n v e r s i o n , wh i c h i s s h o w n as p o in t a in f i gur e 35. w h en this m o de is en t e r e d , al l cir c ui tr y o n th e ad7938/ad79 39 is p o w e r e d do wn excep t f o r t h e r e fer e n c e and r e fer e n c e b u f f er . th e t r ack-and- h o ld g o es i n to h o ld a t this p o in t als o an d r e ma in s in h o ld as l o n g as t h e de vic e is in st an d b y . th e p a r t s r e ma i n in st an d b y un t i l t h e n e xt r i sin g ed g e o f co n v s t p o w e rs u p t h e de vice . th e p o w e r - u p t i m e re qu i r e d d e p e n d s on w h e t he r t h e i n te r n a l or e x te r n a l re f e re nc e is us ed . w i th an ext e r n al r e f e r e n c e , t h e p o w e r - u p time r e q u ir e d is a minim u m of 600 n s , while when usin g t h e in t e r n al re f e re nc e, t h e p o we r - up t i me re qu i r e d i s a m i n i m u m of 7 s . t h e u s e r sh ou l d e n su re t h i s p o we r - up t i m e h a s el a p s e d b e f ore i n it i a t i ng a n ot h e r c o n v e r s i on a s show n i n f i g u r e 3 9 . t h i s ri s i n g ed g e o f co n v s t a l s o places t h e t r ack-and- h o ld b a ck in t o t r ack mo de. full shutdow n mode (pm1 =1; pm0 = 1) w h e n th i s m o de i s p r ogra m m e d , all ci r c ui tr y o n th e ad7938/ad79 39 is p o w e r e d do wn u p on com p letio n o f th e wr i t e op era t io n, i . e . , o n r i sin g e d g e o f wr . the t r ack-and- h o ld en t e rs h o ld m o de a t t h is p o i n t. the p a r t s r e t a in t h e i n fo r m a t ion in t h e con t r o l r e g i s t er w h i l e t h e p a r t is in s h ut do wn. th e ad7938/ad79 39 r e ma in in f u l l s h u t do wn m o de an d t h e track- a nd- h o ld i n h o ld m o de, u n t i l t h e p o w e r ma na gem e n t b i ts ( p m 1 a nd pm0) i n t h e co n t r o l r e g i s t e r a r e cha n g e d . i f a wr i t e t o t h e co n t r o l r e g i s t er o c c u rs w h i l e t h e p a r t is in f u l l sh u t down m o de , a nd t h e p o w e r ma na g e m e n t b i ts a r e cha n g e d to pm0 = pm1 = 0, i . e . , n o r m al mo de , the p a r t beg i n s t o p o w e r - u p o n the wr ri s i n g ed g e a n d th e tra c k - a n d - h o ld r e t u rn s t o tra c k . t o en s u r e t h e p a r t is f u l l y p o w e r e d u p b e fo r e a co n v ersio n is ini t i a te d , t h e p o we r - up t i me of 1 0 ms m i n i m u m s h ou l d b e a l l o we d b e f ore t h e ne x t co n v s t fa l l in g e d ge; o t h e r w is e , i n v a lid da t a is r e a d . n o t e tha t al l p o w e r - u p tim e s q u o t ed a p p l y wi t h a 470 nf c a pa ci t o r o n th e v refin pi n . t power-up 1 1 14 14 busy clkin convst 03715-0-049 a b f i gure 39. a u tosh u t do wn /a utostandby mode
ad7938/ad7939 rev. 0 | page 28 of 32 power vs. throughput rate a b i g ad van t a g e o f p o w e r i n g t h e ad c do w n a f t e r a con v ersio n is t h a t t h e p o w e r co n s um p t ion o f t h e p a r t is sig n if ican t l y r e d u ce d a t lo w e r t h r o u g h p u t ra t e s. w h e n usin g t h e dif f er en t p o w e r m o des, t h e ad7933 /ad7934 a r e o n l y p o w e r e d u p f o r t h e d u ra t i on o f t h e con v ersio n . ther efo r e , t h e a v era g e p o w e r co n s um p t io n p e r c y cle is sig n if ica n t l y r e d u c e d . f i gur e 40 sh o w s a pl ot of t h e p o we r v s . t h e t h ro u g h p ut r a te w h e n op e r a t i n g i n au t o s t a n d b y m o d e f o r b o t h v dd = 5 v a nd 3 v . f o r exa m p l e , if th e maxim u m clki n f r eq uen c y o f 25.5 mh z is us ed t o minimize t h e c o n v ersio n t i m e , this acco un ts f o r o n l y 0.525 s o f th e o v eral l c y c l e time while th e ad7933 /ad7934 r e ma in s in s t a n d b y m o d e fo r th e r e m a in der o f th e c y c l e . i f th e de v i ce s r u n a t a th r o u g h p u t ra t e o f 10 k s p s , f o r e x a m p l e , th en th e o v e r all c y c l e tim e w o u l d b e 100 s. f i g u re 4 1 show s a pl ot of t h e p o we r v s . t h e t h ro u g h p ut r a te w h en op era t i n g in n o r m al mo de fo r b o t h v dd = 5 v a nd 3 v . i n b o t h plo t s, t h e f i gur e s a p ply w h en usin g t h e in t e r n al re f e re nc e. i f an e x te r n a l re f e re nc e i s u s e d , t h e p o we r - up t i me r e d u ces t o 600 n s ; th er ef o r e , the ad7933 /ad7 934 r e ma in s i n s t a n d b y f o r a gr ea t e r tim e in ev e r y c y c l e . a d d i ti o n all y , th e c u r r en t co n s um p t io n, w h e n con v er t i n g , sh o u ld b e lo w e r t h a n th e sp ecif ie d maxim u m o f 2.7 ma o r 2.0 ma wi t h v dd = 5 v or 3 v , re sp e c t i v e ly . throughput (ksps) p o we r (mw) 1.8 0.8 1.0 1.2 1.4 1.6 0 0.6 0.4 0.2 0 2 0 4 0 6 0 8 0 100 120 140 03715-0-042 t a = 25 c v dd = 5v v dd = 3v f i gure 40. p o wer v s . thro ughput in a u t o standb y m o de using int e rn al r e fer e nce throughput (ksps) p o we r (mw) 10 4 5 6 7 8 9 0 3 2 1 0 200 400 600 800 1000 1200 1600 1400 03715-0-043 t a = 25 c v dd = 5v v dd = 3v f i gure 41. p o wer v s . thro ughput in n o rm al mode u s ing i n tern a l r e fe r e nce microprocessor interfacing ad7938/ad7939 to adsp-2 1xx interface f i gur e 42 s h o w s th e ad7938/ad7939 in ter face d t o the ads p - 21xx s e r i es o f d s p s as a m e m o r y ma p p e d de vic e . a sin g le wa i t s t a t e ma y be ne ces s a r y t o in t e r f ace the ad7938 /ad7939 t o t h e ads p -21xx dep e ndin g on t h e cl o c k s p e e d o f t h e ds p . th e wa i t s t a t e c a n b e p r og r a m m ed v i a th e d a ta m e m o r y w a i t s t a t e c o n t ro l re g i ste r of t h e a d sp - 2 1 x x ( s e e t h e a d sp - 2 1 x x f a m i ly u s e r s m a n u a l f o r d e t a i l s ) . t h e f o l l ow i n g i n st r u c t i o n re a d s f rom th e ad7938 /ad7939: mr = d m (ad c ) w h er e ad c is t h e addr es s o f the ad7938 /ad7 939. ad7938/ ad7939* adsp-21xx* wr rd db0 to db11 d0 to d23 a0 to a15 dms ir q2 busy cs convst optional wr rd *additional pins omitted for clarity address bus data bus address decoder 03715-0-045 f i g u re 42. inte r f a c i n g to t h e a d s p - 21x x
ad7938/ad7939 rev. 0 | page 29 of 32 ad7938/ad7939 to adsp-2 1065l interface f i gur e 43 s h o w s a typ i cal i n t e r f ace b e tw e e n t h e ad7938/ad79 39 a nd t h e ads p -21065l s h ar c? p r o c es s o r . this i n t e r f ace is a n exa m ple o f o n e o f t h r e e d m a han d s h a k e mo d e s . t h e ms x co n t r o l line is ac t u al l y thr e e m e mo r y s e lec t l i ne s . in te r n a l a ddr 25-24 a r e de co de d i n to ms 3-0 , t h es e lin e s a r e th en a s se r t e d a s c h i p se l e cts. t h e dm a r 1 (d ma r e q u es t 1) is us e d in t h is s e t u p as t h e in t e r r u p t t o sig n a l t h e end o f c o n v e r s i on . t h e re st of t h e i n te r f a c e i s st a n d a r d h a nd sh a k i n g op e r a t i o n . ad7938/ ad7939* adsp-21065l* wr db0 to db11 d0 to d31 addr 0 to addr 23 ms x dm ar 1 busy cs convst optional wr rd rd * additional pins removed for clarit y address bus address bus data bus address latch address decoder 03715-0-046 f i gure 4 3 . int e r f acing t o th e ads p - 2 10 65 l ad7938/ad7939 to tms32020, tms320c 25, and tms320c5x interface p a ral l e l in t e r f ac es betw een t h e ad7938/ad79 39 a nd t h e t m s32020, t m s320c25, a nd tms320c5x fa mil y o f ds p s a r e s h o w n in f i gur e 44. th e m e m o r y ma p p e d addr es s c h os en f o r th e ad7938 /ad7939 sh o u ld b e c h os en t o fal l in the i/o m e m o r y s p ace o f t h e dsp s . the p a ral l e l in ter face o n t h e ad7938/ad79 39 is fas t en o u g h t o in t e r f ace t o th e t m s32020 wi t h n o extra wa i t sta t es. i f hig h s p e e d g l ue log i c, s u c h as 74 a s de vices, a r e us e d t o dr i v e t h e rd a nd t h e wr lin e s w h en in t e r f acing t o the t m s320c25, t h en a g a i n, n o wa i t sta t es a r e n e ces s a r y . h o w e v e r , if s l o w er log i c is us ed , da t a acces s es ma y b e s l o w ed s u f f i ci e n tl y wh en r e a d in g f r o m , a n d w r i t i n g t o , th e pa r t t o r e q u ir e t h e ins e r t io n o f o n e w a i t st a t e . e x t r a wa i t s t a t es a r e n e ces s a r y wh en usin g th e t m s 320c5x a t t h eir fas t est c l o c k s p eeds (s ee t h e t m s320c5x u s er s g u ide f o r deta ils). d a t a is r e ad f r o m t h e a d c usi n g t h e fol l o w ing in st r u c t io n in d , ad c w h er e d is t h e d a t a m e m o r y a ddr ess and ad c is t h e ad7938/ad79 39 addr es s. ad7938/ ad7939* tms32020/ tms320c25/ tms320c50* wr rd db11 to db0 dmd0 to dmd15 a0 to a15 is ready in t x busy cs en convst optional tms320c25 only r/w strb *additional pins omitted for clarity address bus data bus address decoder 03715-0-047 msc f i gur e 4 4 . int e r f ac ing t o the tms3 2020 / c 2 5 / c 5 x ad7938/ad7939 to 80c18 6 interface f i gur e 45 s h o w s th e ad7938/ad7939 in ter face d t o the 80c186 micr o p r o ces s o r . the 80c186 d m a co n t r o l l er p r o v ides tw o indep e n d en t hi g h s p e e d d m a cha n n e ls w h er e da t a t r an sfer can occur be tw een m e m o r y a n d i/o s p a c e s . e a c h da ta tra n s f e r co n s u m es t w o b u s c y cles , o n e c y cle t o fet c h da t a a nd t h e o t h e r t o s t o r e da t a . af t e r th e ad7938 /a d7939 f i nish a con v ersio n , the b u sy l i ne ge ne r a te s a dm a re qu e s t to c h an n e l 1 ( d rq 1 ) . b e ca us e o f t h e i n t e r r u p t, t h e p r o c es s o r p e r f o r m s a d m a r e ad o p era t ion t h a t a l s o r e s ets t h e i n ter r u p t la t c h. s u f f i cien t p r io r i ty m u s t be as s i gn e d t o th e d m a ch a n n e l t o en s u r e th a t t h e d m a re qu e s t i s s e r v i c e d b e f ore t h e c o m p l e t i on of t h e ne x t co n v ersio n . ad7938/ ad7939* 80c186* wr db0 to db11 ad0 to ad15 a16 to a19 ale drq 1 busy cs qr s convst optional wr rd rd * additional pins omitted for clarit y address/data bus address bus data bus address latch address decoder 03715- 0- 048 f i g u re 45. inte r f a c i n g to t h e 80c 18 6
ad7938/ad7939 rev. 0 | page 30 of 32 application hints grounding and layout the printed circuit board that houses the ad7938/ad7939 should be designed so that the analog and digital sections are separated and confined to certain areas of the board. this facilitates the use of ground planes that can be easily separated. a minimum etch technique is generally best for ground planes since it gives the best shielding. digital and analog ground planes should be joined in only one place, and the connection should be a star ground point established as close to the ground pins on the ad7938/ad7939 as possible. avoid running digital lines under the device as this couples noise onto the die. the analog ground plane should be allowed to run under the ad7938/ ad7939 to avoid noise coupling. the power supply lines to the ad7938/ad7939 should use as large a trace as possible to provide low impedance paths and reduce the effects of glitches on the power supply line. fast switching signals, such as clocks, should be shielded with digital ground to avoid radiating noise to other sections of the board, and clock signals should never run near the analog inputs. avoid crossover of digital and analog signals. traces on opposite sides of the board should run at right angles to each other. this reduces the effects of feedthrough through the board. a microstrip technique is by far the best but is not always possible with a double-sided board. in this technique, the component side of the board is dedicated to ground planes, while signals are placed on the solder side. good decoupling is also important. all analog supplies should be decoupled with 10 f tantalum capacitors in parallel with 0.1 f capacitors to gnd. to achieve the best from these decoupling components, they must be placed as close as possible to the device, ideally right up against the device. the 0.1 f capacitors should have low effective series resistance (esr) and effective series inductance (esi), such as the common ceramic types or surface-mount types, which provide a low impedance path to ground at high frequencies to handle transient currents due to internal logic switching. pcb design guidelines for chip scale package the lands on the chip scale package (cp-32) are rectangular. the printed circuit board pad for these should be 0.1 mm longer than the package land length and 0.05 mm wider than the package land width. the land should be centered on the pad. this ensures that the solder joint size is maximized. the bottom of the chip scale package has a thermal pad. the thermal pad on the printed circuit board should be at least as large as this exposed pad. on the printed circuit board, there should be a clearance of at least 0.25 mm between the thermal pad and the inner edges of the pad pattern. this ensures that shorting is avoided. thermal vias may be used on the printed circuit board thermal pad to improve thermal performance of the package. if vias are used, they should be incorporated in the thermal pad at 1.2 mm pitch grid. the via diameter should be between 0.3 mm and 0.33 mm, and the via barrel should be plated with 1 oz. copper to plug the via. the user should connect the printed circuit board thermal pad to agnd. evaluating the ad7938/ad7939 performance the recommended layout for the ad7938/ad7939 is outlined in the evaluation board documentation. the evaluation board package includes a fully assembled and tested evaluation board, documentation, and software for controlling the board from the pc via the evaluation board controller. the evaluation board controller can be used in conjunction with the ad7938/ ad7939 evaluation board, as well as many other adi evaluation boards ending in the cb designator, to demonstrate/evaluate the ac and dc performance of the ad7938/ad7939. the software allows the user to perform ac (fast fourier transform) and dc (histogram of codes) tests on the ad7938/ ad7939. the software and documentation are on the cd that ships with the evaluation board.
ad7938/ad7939 rev. 0 | page 31 of 32 outline dimensions compliant to jedec standards mo-220-vhhd-2 0.30 0.23 0.18 0.20 ref 0.80 max 0.65 typ 0.05 max 0.02 nom 12 max 1.00 0.85 0.80 seating plane coplanarity 0.08 1 32 8 9 25 24 16 17 0.50 0.40 0.30 3.50 ref 0.50 bsc pin 1 indicator top view 5.00 bsc sq 4.75 bsc sq 3.45 3.30 sq 3.15 pin 1 indicator 0.60 max 0.60 max 0.25 min exposed pad (bottom view) f i gure 46. 3 2 -l ead l e ad f r a m e ch ip s c a l e p a ck ag e [lfcs p ] 5 mm 5 m m b o d y (cp - 3 2 -3) di me nsio ns sho w n i n mi ll im e t e r s 0. 4 5 0. 3 7 0. 3 0 0. 80 bs c 7. 00 sq 9.00 sq 1 24 25 32 8 9 17 16 1. 20 ma x 0.75 0.60 0.45 1.05 1.00 0.95 0.20 0.09 0.08 max coplanarity seating plane 0 min 7 3. 5 0 0.15 0.05 view a rotated 90 ccw view a pin 1 top v ie w (pins down) compliant to jedec standards ms-026aba f i g u re 47. 3 2 -l ead thin plas t i c q u ad flat p a ck ag e [ t qfp ] (su - 32-2) di me nsio ns sho w n i n mi ll im e t e r s
ad7938/ad7939 rev. 0 | page 32 of 32 ordering guide model temperature r a nge linearity error (lsb) 1 package descri ptions package option ad7938bcp C40c to +85c 1 32-lead lfcsp cp-32-3 ad7938bcp-ree l C40c to +85c 1 32-lead lfcsp cp-32-3 ad7938bcp-ree l7 C40c to +85c 1 32-lead lfcsp cp-32-3 ad7938bcpz 2 C40c to +85c 1 32-lead lfcsp cp-32-3 ad7938bcpz-r eel7 2 C40c to +85c 1 32-lead lfcsp cp-32-3 ad7938bsu C40c to +85c 1 32-lead tqfp su-32-2 ad7938bsu-re el C40c to +85c 1 32-lead tqfp su-32-2 ad7938bsu-re el7 C40c to +85c 1 32-lead tqfp su-32-2 ad7938bsuz 2 C40c to +85c 1 32-lead tqfp su-32-2 ad7938bsuz-r eel7 2 C40c to +85c 1 32-lead tqfp su-32-2 eval-ad7938c b 3 evaluation bo ar d ad7939bcp C40c to +85c 1 32-lead lfcsp cp-32-3 ad7939bcp-ree l C40c to +85c 1 32-lead lfcsp cp-32-3 ad7939bcp-ree l7 C40c to +85c 1 32-lead lfcsp cp-32-3 ad7939bcpz 2 C40c to +85c 1 32-lead lfcsp cp-32-3 ad7939bcpz-r eel7 2 C40c to +85c 1 32-lead lfcsp cp-32-3 ad7939bsu C40c to +85c 1 32-lead tqfp su-32-2 ad7939bsu-re el C40c to +85c 1 32-lead tqfp su-32-2 ad7939bsu-re el7 C40c to +85c 1 32-lead tqfp su-32-2 ad7939bsuz 2 C40c to +85c 1 32-lead tqfp su-32-2 ad7939bsuz-r eel7 2 C40c to +85c 1 32-lead tqfp su-32-2 eval-ad7939c b 3 evaluation bo ar d eval-control brd2 4 controll er boar d 1 linearity error here re fer s to integral li nearity error. 2 z = pb-free part. 3 this can be us ed a s a s t and a l o ne e v aluatio n bo ard o r in conjunct i o n with the e v al uatio n bo ard co ntro l le r f o r e v al ua tio n /d e m o n s tration purpose s . 4 e v al uation board control ler. this board is a comp l e te unit al lowing a pc to control a n d c o m m u n i ca t e wi t h a ll an a l o g d e vi ces ev a l ua t i o n boa r ds en di n g i n t h e cb designators. the fo llowing needs to b e or dered to obtain a complete evaluation kit: the adc eval uation board (e.g . eval ad7938c b), t h e e v al- c on tr ol b r d 2 a n d a 12 v ac trans f o r me r. s e e re le vant e v al uatio n bo ard te chnical no te f o r mo re detail s . ?2004 a n alo g de vices, inc. all rig h ts reserv ed. tra d ema r ks and registered tra d ema r ks are the prop erty of their respective owners . d03715C0C 10/04(0)

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